Patents by Inventor Sandeep Nijhawan

Sandeep Nijhawan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020975
    Abstract: Described herein are systems and methods for the management and control of electrolyte within confined electrochemical cells or groups (e.g. stacks) of connected electrochemical cells, for example, in an electrolyzer. Various embodiments of systems and methods provide for the elimination of parasitic conductive paths between cells, and/or precise passive control of fluid pressures within cells. In some embodiments, a fixed volume of electrolyte is substantially retained within each cell while efficiently collecting and removing produced gases or other products from the cell.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: AQUAHYDREX, INC.
    Inventors: Eric SEYMOUR, Gregory KUMOR, Erik T. HERRERA, Byron J. BURKILL, David COX, Sandeep NIJHAWAN, Cameron TAVENER-SMITH, Wayne Richard HEMZACEK, Nathaniel Martin SCHUH
  • Publication number: 20200365953
    Abstract: In an aspect, provided is an alkaline rechargeable battery comprising: i) a battery container sealed against the release of gas up to at least a threshold gas pressure, ii) a volume of an aqueous alkaline electrolyte at least partially filling the container to an electrolyte level; iii) a positive electrode containing positive active material and at least partially submerged in the electrolyte; iv) an iron negative electrode at least partially submerged in the electrolyte, the iron negative electrode comprising iron active material; v) a separator at least partially submerged in the electrolyte provided between the positive electrode and the negative electrode; vi) an auxiliary oxygen gas recombination electrode electrically connected to the iron negative electrode by a first electronic component, ionically connected to the electrolyte by a first ionic pathway, and exposed to a gas headspace above the electrolyte level by a first gas pathway.
    Type: Application
    Filed: December 27, 2018
    Publication date: November 19, 2020
    Applicant: STAQ ENERGY, INC.
    Inventors: Ai Quoc PHAM, Sandeep NIJHAWAN, Aswin K. MANOHAR, Kevin Van GALLOWAY, Chenguang YANG, Eric E. BENSON, Lang McHARDY, Tim RACKERS
  • Patent number: 9932670
    Abstract: A method and apparatus for removing deposition products from internal surfaces of a processing chamber, and for preventing or slowing growth of such deposition products. A halogen containing gas is provided to the chamber to etch away deposition products. A halogen scavenging gas is provided to the chamber to remove any residual halogen. The halogen scavenging gas is generally activated by exposure to electromagnetic energy, either inside the processing chamber by thermal energy, or in a remote chamber by electric field, UV, or microwave. A deposition precursor may be added to the halogen scavenging gas to form a deposition resistant film on the internal surfaces of the chamber. Additionally, or alternately, a deposition resistant film may be formed by sputtering a deposition resistant metal onto internal components of the processing chamber in a PVD process.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 3, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Jie Su, Lori D. Washington, Sandeep Nijhawan, Olga Kryliouk, Jacob Grayson, Sang Won Kang, Dong Hyung Lee, Hua Chung
  • Patent number: 9644267
    Abstract: A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, a metal organic chemical vapor deposition (MOCVD) process is used to deposit a Group III-nitride film on a plurality of substrates. A Group III precursor, such as trimethyl gallium, trimethyl aluminum or trimethyl indium and a nitrogen-containing precursor, such as ammonia, are delivered to a plurality of straight channels which isolate the precursor gases. The precursor gases are injected into mixing channels where the gases are mixed before entering a processing volume containing the substrates. Heat exchanging channels are provided for temperature control of the mixing channels to prevent undesirable condensation and reaction of the precursors.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: May 9, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Brian H. Burrows, Alexander Tam, Ronald Stevens, Kenric T. Choi, James David Felsch, Jacob Grayson, Sumedh Acharya, Sandeep Nijhawan, Lori D. Washington, Nyi O. Myo
  • Patent number: 9466499
    Abstract: A substrate having a plurality of site-isolated regions defined thereon is provided. A first electrochromic material, or a first electrochromic device stack, is formed above a first of the plurality of site-isolated regions using a first set of processing conditions. A second electrochromic material, or a second electrochromic device stack, is formed above a second of the plurality of site-isolated regions using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 11, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Minh Huu Le, Minh Anh Nguyen, Sandeep Nijhawan
  • Publication number: 20160111603
    Abstract: Provided are light emitting diodes (LEDs) and methods of fabricating such LEDs. Specifically, an LED has an epitaxial stack and current distribution layer disposed on and interfacing the epitaxial stack. The current distribution layer includes indium oxide and zinc oxide such that the concentration of indium oxide is between about 5% and 15% by weight. During fabrication, the current distribution layer is annealed at a temperature of less than about 500° C. or even at less than about 400° C. These low anneal temperature helps preserving the overall thermal budget of the LED while still yielding a current distribution layer having a low resistivity and low adsorption. A particular composition and method of forming the current distribution layer allows using lower annealing temperatures. In some embodiments, the current distribution layer is sputtered using indium oxide and zinc oxide targets at a pressure of less than 5 mTorr.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 21, 2016
    Inventors: Jianhua Hu, Ben Cardozo, Minh Huu Le, Sandeep Nijhawan, J.H. Yeh
  • Patent number: 9306126
    Abstract: Transparent conductive layers usable as ohmic contacts for III-V semiconductors with work functions between 4.1 and 4.7 eV are formed by annealing layers of transparent oxide with thin (0.1-5nm) layers of conductive metal. When the layers interdiffuse during the annealing, some of the conductive metal atoms remain free to reduce resistivity and others oxidize to reduce optical absorption. Examples of the transparent oxides include indium-tin oxide, zinc oxide, and aluminum zinc oxide with up to 5 wt % Al. Examples of the metals include aluminum and titanium. The work function of the transparent conductive layer can be tuned to match the contacted semiconductor by adjusting the ratio of metal to transparent oxide.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: April 5, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Jianhua Hu, Heng-Kai Hsu, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Patent number: 9246062
    Abstract: Transparent ohmic contacts to p-GaN and other high-work-function (?4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 26, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Jianhua Hu, Heng Kai Hsu, Tong Ju, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Publication number: 20160013367
    Abstract: Transparent conductive layers usable as ohmic contacts for III-V semiconductors with work functions between 4.1 and 4.7 eV are formed by annealing layers of transparent oxide with thin (0.1-5 nm) layers of conductive metal. When the layers interdiffuse during the annealing, some of the conductive metal atoms remain free to reduce resistivity and others oxidize to reduce optical absorption. Examples of the transparent oxides include indium-tin oxide, zinc oxide, and aluminum zinc oxide with up to 5 wt % Al. Examples of the metals include aluminum and titanium. The work function of the transparent conductive layer can be tuned to match the contacted semiconductor by adjusting the ratio of metal to transparent oxide.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 14, 2016
    Inventors: Jianhua Hu, Heng-Kai Hsu, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Publication number: 20150318446
    Abstract: A ternary transparent conductive oxide, indium zinc oxide (IZO), is formed as a thin film by co-sputtering zinc oxide with indium oxide at a deposition temperature between 25 and 200 C. Optionally, up to 1-2% Al may be added by various methods. The layers may be annealed at temperatures between 200 and 400 C. Measurements of IZO with 75-85 wt % In2O3 showed low resistivity and low visible absorbance, both of which were thermally stable up to 400 C.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Applicant: Intermolecular, Inc.
    Inventors: Jianhua Hu, Heng Kai Hsu, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Publication number: 20150311397
    Abstract: Transparent ohmic contacts to p-GaN and other high-work-function (?4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 29, 2015
    Applicant: INTERMOLECULAR, INC.
    Inventors: Jianhua Hu, Heng Kai Hsu, Tong Ju, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Patent number: 9012261
    Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Sang Lee, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Publication number: 20150091032
    Abstract: Diffusion of silver from LED reflector layers is blocked by 10-50 nm barrier layers of nickel-titanium (NiTi) alloys. Optionally, the alloys also include one or more of tungsten (W), niobium (Nb), aluminum (Al), vanadium (V), tantalum (Ta), or chromium (Cr). These barriers may omit the noble-metal (e.g., platinum or gold) cap used with silver barriers based on other materials.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 2, 2015
    Applicant: Intermolecular, Inc.
    Inventors: Jianhua Hu, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Patent number: 8859406
    Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25-0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: October 14, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Sang Lee, Wei Liu, Sandeep Nijhawan, Jeroen Van Duren
  • Patent number: 8859405
    Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25?0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 14, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Sang Lee, Wei Liu, Sandeep Nijhawan, Jeroen Van Duren
  • Patent number: 8853059
    Abstract: A method for high temperature selenization of Cu—In—Ga metal precursor films comprises ramping the precursor film to a temperature between about 350 C and about 450 C in an inert gas and at a pressure between about 1 atmosphere and about 2 atmospheres. A partial selenization is performed at a temperature between about 350 C and about 450 C in a Se-containing atmosphere. The film is then ramped to a temperature between about 450 C and about 550 C in an inert gas and at a pressure between about 1 atmosphere and about 2 atmospheres, followed by an additional selenization step at a temperature between about 450 C and about 550 C in a Se-containing atmosphere. The film is then annealed at a temperature between about 550 C and about 650 C in an inert gas.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Jeroen Van Duren, Sandeep Nijhawan
  • Publication number: 20140272112
    Abstract: Embodiments provided herein describe methods and systems for evaluating electrochromic material processing conditions. A substrate having a plurality of site-isolated regions defined thereon is provided. A first electrochromic material, or a first electrochromic device stack, is formed above a first of the plurality of site-isolated regions using a first set of processing conditions. A second electrochromic material, or a second electrochromic device stack, is formed above a second of the plurality of site-isolated regions using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.
    Type: Application
    Filed: December 27, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Minh Huu Le, Minh Anh Nguyen, Sandeep Nijhawan
  • Publication number: 20140261660
    Abstract: Methods are used to develop and evaluate new materials and deposition processes for use as TCO materials in HJCS solar cells. The TCO layers allow improved control over the uniformity of the TCO conductivity and interface properties, and reduce the sensitivity to the texture of the wafer. In Some embodiments, the TCO materials include indium, zinc, tin, and aluminum.
    Type: Application
    Filed: November 18, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular , Inc.
    Inventors: Jianhua Hu, Heng-Kai Hsu, Minh Huu Le, Sandeep Nijhawan
  • Publication number: 20140273340
    Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.
    Type: Application
    Filed: December 2, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Sang Lee, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Patent number: 8835961
    Abstract: Devices are described including a first component and a second component, wherein the first component comprises a Group III-N semiconductor and the second component comprises a bimetallic oxide containing tin, having an index of refraction within 15% of the index of refraction of the Group III-N semiconductor, and having negligible extinction coefficient at wavelengths of light emitted or absorbed by the Group III-N semiconductor. The first component is in optical contact with the second component. Exemplary bimetallic oxides include Sn1-xBixO2 where x?0.10, Zn2SnO2, Sn1-xAlxO2 where x?0.18, and Sn1-xMgxO2 where x?0.16. Methods of making and using the devices are also described.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Philip Kraus, Minh-Huu Le, Sandeep Nijhawan