Patents by Inventor Sang Choon Ko

Sang Choon Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160225631
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
    Type: Application
    Filed: April 8, 2016
    Publication date: August 4, 2016
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Hoon JUN, Sang Choon KO, Seok-Hwan MOON, Woojin CHANG, Sung-Bum BAE, Young Rak PARK, Je Ho NA, Jae Kyoung MUN, Eun Soo NAM
  • Patent number: 9362744
    Abstract: The inventive concept relates to a system supplying a constant current direct current power to serial loads connected in series with one another. The inventive concept is constituted by a constant current source power supply unit outputting a predetermined direct current, a load connection unit having the same rated current characteristic as the constant current source, a load connection unit having a rated current characteristic smaller than the constant current source, a load connection unit having a rated current characteristic greater than the constant current source, a load connection unit having a rated current characteristic greater or smaller than the constant current source and a circuit controlling or protecting them.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 7, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong il Jun, Sang Choon Ko, Jae Kyoung Mun, Dae Woo Lee, Kyu-Seok Lee, Ho Young Kim, Chul Won Ju
  • Patent number: 9337121
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: May 10, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Hoon Jun, Sang Choon Ko, Seok-Hwan Moon, Woojin Chang, Sung-Bum Bae, Young Rak Park, Je Ho Na, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 9293689
    Abstract: A piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: March 22, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Hoon Jun, Sang Choon Ko, Jong Tae Moon
  • Publication number: 20150380354
    Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Byoung-Gue MIN, Sang Choon KO, Jong-Won LIM, Hokyun AHN, Hyung Sup YOON, Jae Kyoung MUN, Eun Soo NAM
  • Patent number: 9159612
    Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 13, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Byoung-Gue Min, Sang Choon Ko, Jong-Won Lim, Hokyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 9159583
    Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 13, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Choon Ko, Jae Kyoung Mun, Woojin Chang, Sung-Bum Bae, Young Rak Park, Chi Hoon Jun, Seok-Hwan Moon, Woo-Young Jang, Jeong-Jin Kim, Hyungyu Jang, Je Ho Na, Eun Soo Nam
  • Patent number: 9136396
    Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 15, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Choon Ko, Jae Kyoung Mun, Byoung-Gue Min, Young Rak Park, Hokyun Ahn, Jeong-Jin Kim, Eun Soo Nam
  • Patent number: 9136347
    Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 15, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Rak Park, Sang Choon Ko, Woojin Chang, Jae Kyoung Mun, Sung-Bum Bae
  • Publication number: 20150194363
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
    Type: Application
    Filed: July 7, 2014
    Publication date: July 9, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Chi Hoon JUN, Sang Choon KO, Seok-Hwan MOON, Woojin CHANG, Sung-Bum BAE, Young Rak PARK, Je Ho NA, Jae Kyoung MUN, Eun Soo NAM
  • Publication number: 20150187599
    Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.
    Type: Application
    Filed: June 20, 2014
    Publication date: July 2, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Choon KO, Jae Kyoung MUN, Woojin CHANG, Sung-Bum BAE, Young Rak PARK, Chi Hoon JUN, Seok-Hwan MOON, Woo-Young JANG, Jeong-Jin KIM, Hyungyu JANG, Je Ho NA, Eun Soo NAM
  • Publication number: 20150187886
    Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.
    Type: Application
    Filed: June 23, 2014
    Publication date: July 2, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Young Rak PARK, Sang Choon KO, Woojin CHANG, Jae Kyoung MUN, Sung-Bum BAE
  • Patent number: 9024511
    Abstract: The present inventive concept discloses an impact-type piezoelectric micro power generator. The impact-type piezoelectric micro power generator may comprise a base having a cavity and at least one stop area adjacent to the cavity; a frame fastened to the base; a vibrating body comprising a plurality of first vibrating beams extended from the frame toward a top of the cavity, an impact beam connected to between first tips of the plurality of first vibrating beams and extended onto the stop area, and a second vibrating beam extended from the impact beam to between the plurality of first vibrating beams, the second vibrating beam having a second tip; and a piezoelectric device disposed on one of a top and a bottom of the second vibrating beam and the impact beam, the piezoelectric device generating electric power according to impacts of the vibrating body to the stop area and bending of the impact beam and the second vibrating beam.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: May 5, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chi Hoon Jun, Sang Choon Ko, Seok-Hwan Moon, Kwang-Seong Choi
  • Patent number: 8941231
    Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: January 27, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Rak Park, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 8937002
    Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: January 20, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Bum Bae, Eun Soo Nam, Jae Kyoung Mun, Sung Bock Kim, Hae Cheon Kim, Chull Won Ju, Sang Choon Ko, Jong-Won Lim, Ho Kyun Ahn, Woo Jin Chang, Young Rak Park
  • Publication number: 20140363937
    Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.
    Type: Application
    Filed: June 18, 2014
    Publication date: December 11, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Woo Jin CHANG, Jong-Won LIM, Ho Kyun AHN, Sang Choon KO, Sung Bum BAE, Chull Won JU, Young Rak PARK, Jae Kyoung MUN, Eun Soo NAM
  • Publication number: 20140213045
    Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Bum BAE, Eun Soo NAM, Jae Kyoung MUN, Sung Bock KIM, Hae Cheon KIM, Chull Won JU, Sang Choon KO, Jong-Won LIM, Ho Kyun AHN, Woo Jin CHANG, Young Rak PARK
  • Patent number: 8772833
    Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: July 8, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Woo Jin Chang, Jong Won Lim, Ho Kyun Ahn, Sang Choon Ko, Sung Bum Bae, Chull Won Ju, Young Rak Park, Jae Kyoung Mun, Eun Soo Nam
  • Publication number: 20140167070
    Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.
    Type: Application
    Filed: July 10, 2013
    Publication date: June 19, 2014
    Inventors: Young Rak PARK, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
  • Publication number: 20140159049
    Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
    Type: Application
    Filed: May 30, 2013
    Publication date: June 12, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Choon KO, Jae Kyoung Mun, Byoung-Gue Min, Young Rak Park, Hokyun Ahn, Jeong-Jin Kim, Eun Soo Nam