Abstract: A method for forming a super contact in a semiconductor device is disclosed. The method enables forming a barrier film selectively on the silicon substrate, leaving the metal contact exposed for perfect isolation of the metal pad from the silicon substrate after formation of the super contact.

Abstract: Provided are a biosensor and a method of fabricating the same. The biosensor has a transistor structure including a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode, source and drain electrodes formed on the gate insulating layer, and a channel region formed between the source and drain electrodes. Here, the channel region includes an active layer formed of an active polymer sensing an antigen-antibody reaction and a hydrophilic nano particle. The active layer is formed through direct printing, for example, inkjet printing. The biosensor having such a structure can be increased in reactivity between an antigen and an antibody and hydrophilicity to improve the sensor's characteristics, fabricated in a large-area process using direct printing, and further facilitates formation of devices on various substrates formed of, for example, plastic.

Abstract: Disclosed is a method for forming a metal line. The method includes preparing a semiconductor substrate having a first metal line, performing an oxidation process with respect to the first metal line, performing an oxide removal process to remove an oxide generated in the oxidation process, forming an etch stop layer on the metal line, forming an interlayer dielectric layer on the first metal line, and forming a damascene pattern on the interlayer dielectric layer, and forming a second metal line, which is connected with the first metal line, in the damascene pattern. The oxidation process for the first metal line can include a hydrogen peroxide treatment process using a solution including oxygen. The oxide removal process can be performed by using an oxalic acid (HOOC-COOH) solution.

Abstract: A method of forming a metal wiring of a semiconductor device, and devices thereof. A method of forming a metal wiring, and devices thereof, may maximize semiconductor yield by substantially removing oxide on and/or over a trench and/or by substantially removing a by-product that may remain on and/or over a surface of a wafer. A method of forming a metal wiring of a semiconductor may include forming a dielectric layer on and/or over a metal wiring. A method of forming a metal wiring of a semiconductor may include forming a contact hole, which may expose a partial surface of metal wiring, on and/or over a dielectric layer. A method of forming a metal wiring of a semiconductor may include performing an oxide removing process on and/or over an inner side of a contact hole, and/or performing a by-product removing process on and/or over an inner side wall of a trench.

Abstract: Provided is a method for manufacturing a semiconductor device. An insulation layer is formed on a bottom structure of a semiconductor substrate. Then, a trench and a via hole are formed by selectively etching the insulation layer, and a copper layer is deposited to fill the via hole and the trench. Next, a copper line is formed by a CMP (chemical mechanical polishing) process to planarize the copper layer, and a plasma process is performed to form a plasma-treated surface layer of the semiconductor substrate. The plasma-treated surface layer is then removed.

Abstract: A semiconductor device includes a substrate formed with a predetermined trench, a plurality of devices fixed into the trench, an etch stop layer on an entire surface of the substrate including the devices while selectively exposing the devices, an interlayer dielectric layer on the etch stop layer, in which the interlayer dielectric layer includes a predetermined via hole and a predetermined trench, and a via plug and a metal line formed on the interlayer dielectric layer while filling the via hole and the trench.

Abstract: Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device, a silicon epitaxial layer formed on and/or over the first device, a second device formed on and/or over the silicon epitaxial layer, and a connection via formed through the silicon epitaxial layer, which may electrically interconnect the first device and the second device. According to embodiments, a method for fabricating a semiconductor device may include forming a first device, forming a silicon epitaxial layer on and/or over the first device, forming a connection via through the silicon epitaxial layer, and forming a second device on and/or over the silicon epitaxial layer such that the second device may be electrically connected to the connection via.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.

Abstract: A CMOS Image Sensor (CIS) that minimizes light loss and achieves maximized performance. The CIS includes a plurality of metal wirings provided on and/or over a semiconductor substrate and surrounded, respectively, by a dielectric layer, a silicon layer deposited on and/or over the plurality of metal wirings, a photodiode and a plurality of transistors provided at the silicon layer, a color filter formed on and/or over the transistors, and via-contacts penetrated through the silicon layer, the photodiode being connected to the plurality of metal wirings by the via-contacts and gap-fillers. The photodiodes and the transistors are formed after forming the metal line.

Abstract: Embodiments relate to a semiconductor device and to a method of fabricating a semiconductor device. According to embodiments, reliability may be enhanced by removing oxide from a barrier metal surface. According to embodiments, a method may include forming an insulating layer on and/or over a metal layer formed on and/or over a substrate, forming a via hole by etching the insulating layer to expose the metal layer, forming a trench by etching a portion of the insulating layer in an area having the via hole formed therein, forming a barrier metal layer on and/or over the insulating layer including the trench and the via hole, performing plasma processing on the barrier metal layer, and forming a seed Cu layer on the barrier metal layer.

Abstract: An image sensor and a method for fabricating the same having enhanced sensivity. The image sensor enhances sensitivity and minimizes optical loss by isolating color filters from each other using a metal that has superior light reflection properties while having no effect on the color filters during deposition of the metal.

Abstract: A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounted on the substrate to have a space between one or more of the chips and an edge of the substrate, an insulating layer covering the chips, the insulating layer having via holes exposing portions of the at least two chips and a trench between the via holes, the insulating layer having at least two hole patterns within the space, and a metal layer filling the via holes and the trench.

Abstract: A method of fabricating a semiconductor device that may include at least one of the following steps: Forming a lower metal wiring on and/or over a semiconductor substrate. Forming an interlayer insulating film having a damascene hole on and/or over the semiconductor substrate and the lower metal wiring. Forming an anti-diffusion film on and/or over the exposed lower metal wiring below the damascene hole and/or on side surfaces of the damascene hole. Selectively removing the anti-diffusion film formed on and/or over the exposed lower metal wiring at the bottom of the damascene hole using a plasma process that uses an inert gas.

Abstract: A BOAC/COA of a semiconductor device is manufactured by forming a conductive pad over a semiconductor device, forming a passivation oxide film over the semiconductor device including the conductive pad, forming an oxide film over the entire surface of the conductive pad and the passivation oxide film, forming an oxide film pattern defining a bond pad region on the conductive pad, sequentially forming a barrier film and a metal seed layer over the oxide film pattern, the passivation oxide film and the conductive pad, forming a metal layer over the metal seed layer, planarizing the metal layer exposing the oxide film pattern and portions of the barrier film and the metal seed layer, and removing the oxide film pattern by an etching process.

Abstract: A PDP driving circuit for a stable operation of a ramp pulse. A capacitor having a temperature characteristic opposite to a temperature characteristic of a part coupled to a switch that operates as a constant current source for generation of a ramp pulse is arranged in the driving circuit for generating a ramp pulse. The ramp pulse linearly increases or decreases a panel voltage of the PDP with respect to time. Parts having opposite temperature characteristics are coupled in parallel to control variation of a gradient of the ramp pulse so that values of the parts may not be varied depending on the temperature changes. Thus, stable operation of the ramp pulse is obtained.

Abstract: In driving a plasma display device, a driving time is accumulatively calculated, and the number of subfields to which a main reset waveform for initializing every discharge cell is supplied in a first frame in which the accumulative driving time is longer than a reference time is larger than the number of subfields to which the main reset waveform is supplied in a second frame in which the accumulative driving time is shorter than the reference time. By increasing the number of subfields to which the main reset waveform is supplied in a single frame with an increase in the accumulative driving time of the plasma display device, a discharge delay can be reduced by using priming particles formed by a main reset.

Abstract: A plasma display includes a plasma display panel having a plurality of first electrodes, a plurality of second electrodes, a plurality of third electrodes crossing the first and second electrodes, and discharge cells corresponding to electrode crossings, and a controller configured to control reset, address and sustain operations for a plurality of weighted subfields, and to control a misfire prevention operation, the misfire prevention operation occurring before a main reset operation in a subfield that includes the main reset operation.

Abstract: A method for forming a semiconductor device comprising forming an inter-layer dielectric (ILD) layer on a semiconductor substrate; forming a first trench and second trench in a cell area on the ILD layer, wherein the second trench has a width which is wider than the first trench; forming a first metal layer on the substrate, such that the first metal layer fills the first trench and does not entirely fill the second trench; performing a planarization process on the first metal layer such that the surface of the first metal layer in the first trench and the surface of the substrate has a height which is different than the height of the surface of the first metal layer in the second trench; and forming a plurality of align key and overlay key areas by forming a second metal layer on the surface of the substrate and first metal layer.

Abstract: An electroplating apparatus and method are provided. The electrolysis plating apparatus includes an electrolytic cell, and copper electrode, a wafer electrode, and a magnetic field generator.

Abstract: A method for manufacturing a semiconductor device is provided. The method can include forming a pattern for a copper line on a semiconductor substrate, forming a barrier metal layer on the pattern, removing a natural oxide layer from the barrier metal layer using a basic compound, and depositing copper ions on the barrier metal layer. A copper seed layer is not necessary.