Abstract: A semiconductor device according to an embodiment includes a first metal wiring formed on a semiconductor substrate; a first dielectric barrier layer formed on the first metal wiring; an inter-layer dielectric (ILD) layer formed on the first dielectric barrier layer; a plurality of second metal wirings formed on the ILD layer; and at least one hole formed in the ILD layer in regions between second metal wirings.

Abstract: An image sensor is provided. The image sensor includes a transistor region over a substrate, an interlayer insulating layer having a via hole over the transistor region, a silicon layer over the interlayer insulating layer, and a photodiode over the silicon layer.

Abstract: A semiconductor device includes a substrate formed with a predetermined trench, a plurality of devices fixed into the trench, an etch stop layer on an entire surface of the substrate including the devices while selectively exposing the devices, an interlayer dielectric layer on the etch stop layer, in which the interlayer dielectric layer includes a predetermined via hole and a predetermined trench, and a via plug and a metal line formed on the interlayer dielectric layer while filling the via hole and the trench.

Abstract: A method and apparatus for fabricating a semiconductor device are provided. First plasma ions are introduced into a process chamber including a semiconductor substrate to amorphize the semiconductor substrate. An inert gas is introduced into the process chamber to purge the first plasma ions. Second plasma ions are introduced into the process chamber to remove impurities formed on the semiconductor substrate. The second plasma ions can be hydrogen ions. Since a PAI process and a cleaning process are performed in a single chamber, process efficiency improves. In addition, a cleaning process using hydrogen ions can reduce damage on the surface of the semiconductor substrate.

Abstract: Provided is a method for fabricating a metal line of a semiconductor device. In a method according to one embodiment, an interlayer insulating layer is formed on a semiconductor substrate. After that, a first trench and a second trench having a wider width than that of the first trench are formed in the interlayer insulating layer. A seed layer is formed on the semiconductor substrate including the first and second trenches, and a first copper layer is formed on the seed layer. Subsequently, the first copper layer is polished until the interlayer insulating layer is exposed, and a second copper layer is formed on the first copper layer. Then, the second copper layer is planarized to form a copper line.

Abstract: There is provided an organic electroluminescence device employing a multi-layered pixel electrode and a method of fabricating the same. The organic electroluminescence device comprises a substrate, a first pixel electrode located in a predetermined area on the substrate, and a second pixel electrode located on the first pixel electrode and entirely covering the first pixel electrode. Thus, the film breakdown due to the galvanic phenomenon is precluded.

Abstract: A method of forming a copper interconnection including at least one of: Forming an interlayer dielectric layer over a silicon substrate. Forming a plurality of via holes and trench patterns in an interlayer dielectric layer; forming a photoresist pattern over an interlayer dielectric layer between a plurality of via hole and trench patterns. Performing an electroplating process on a silicon substrate so that copper may be filled in a plurality of via holes and trench patterns. Planarizing a copper layer so that a photoresist pattern is removed.

Abstract: Provided is a method for manufacturing a semiconductor device. An insulation layer is formed on a bottom structure of a semiconductor substrate. Then, a trench and a via hole are formed by selectively etching the insulation layer, and a copper layer is deposited to fill the via hole and the trench. Next, a copper line is formed by a CMP (chemical mechanical polishing) process to planarize the copper layer, and a plasma process is performed to form a plasma-treated surface layer of the semiconductor substrate. The plasma-treated surface layer is then removed.

Abstract: A method for displaying gray levels in a PDP by generating gray data corresponding to externally input image signals and displaying the gray data on the PDP is disclosed. The method comprises generating reference signals based on the image signals, determining a spread filter value according to states of the reference signals, applying the spread filter value to the gray data and generating final gray data, and displaying the final gray data on the PDP. The present invention reduces contour noise generated between moving pictures' adjacent grays.

Abstract: In a plasma display panel, sustain discharge pulses having a first voltage and a second voltage, which is a negative voltage of the first voltage, may be applied to a scan electrode when a sustain electrode is biased with the ground voltage during a sustain period. The second voltage is generated without providing an additional power source but rather by a sustain discharge supply circuit, supplied with the first voltage, that repeatedly performs switching operations to generate the second voltage.

Abstract: Reset, address, and sustain operations of a plasma display device are performed by applying a driving waveform to a scan electrode while biasing a sustain electrode at a ground voltage. Then a driving board for driving the sustain electrode may be eliminated. In addition, a discharge between the sustain electrode and the scan electrode as well as between an address electrode and the scan electrode may be ensured in an address period by accumulating positive wall charges on the sustain electrode at an end of a falling period of a reset period.

Abstract: In a Plasma Display Panel (PDP), during an address period, a plurality of scan electrodes are divided into a plurality of groups having a first and a second group, and, during an address period, a first scan pulse and a second scan pulse succeeding the first scan pulse are supplied to at least one scan electrode among the first group of scan electrodes. The first scan pulse is supplied to at least one scan electrode among the second group of scan electrodes while the second pulse is supplied to at least one scan electrode among the first group of scan electrodes, and the second scan pulse succeeding the first scan pulse is supplied to at least one scan electrode among the second group of scan electrodes.

Abstract: A chemical vapor deposition unit is invented for forming a uniform thin film over the entire surface of a substrat by the vapor-deposition. The chemical vapor deposition unit comprises a reaction chamber isolated from the outside and kept under vacuum, a susceptor, on which at least one substrate is placed, installed in the reaction chamber such that it can rotate, and an injector, including independently formed first and second gas passages, and first and second gas injecting pipes that communicate with the respective gas passages and respective outlets, for injecting respective first and second gases onto the susceptor, the injector injecting the different gases independently. The injector further comprises a gas injecting part for communicating with the second gas passage so that only the second gas, which is a non-reactive carrier gas, is injected in a central region of the susceptor.

Abstract: A method for driving a plasma display panel including a first electrode, a second electrode, and an address electrode utilizing a plurality of subfields, including a first subfield and a second subfield. A voltage difference between the address electrode and the first electrode in a selected discharge cell in an address period of the first subfield, and a voltage difference between the address electrode and the first electrode in the selected discharge cell in the address period of the second subfield, are different.

Abstract: There is provided an organic electroluminescence device employing a multi-layered pixel electrode and a method of fabricating the same. The organic electroluminescence device comprises a substrate, a first pixel electrode located in a predetermined area on the substrate, and a second pixel electrode located on the first pixel electrode and entirely covering the first pixel electrode. Thus, the film breakdown due to the galvanic phenomenon is precluded.

Abstract: A PDP driving circuit for a stable operation of a ramp pulse. A capacitor having a temperature characteristic opposite to a temperature characteristic of a part coupled to a switch that operates as a constant current source for generation of a ramp pulse is arranged in the driving circuit for generating a ramp pulse. The ramp pulse linearly increases or decreases a panel voltage of the PDP with respect to time. Parts having opposite temperature characteristics are coupled in parallel to control variation of a gradient of the ramp pulse so that values of the parts may not be varied depending on the temperature changes. Thus, stable operation of the ramp pulse is obtained.

Abstract: A method for driving a plasma display panel having a front substrate and a rear substrate facing and spaced apart from each other, and n common electrode lines, n scan electrode lines, and m address electrode lines arranged between the front and rear substrates (m and n are integers greater than 1), the common electrode lines and the scan electrode lines being parallel to each other, the address electrode lines being orthogonal to the scan electrode lines, to define pixels at respective intersections, the method including, (1) in order to distribute the n common electrode lines to k common electrode groups (k is an integer of greater than or equal to 2), setting (p+k·j)th common electrode lines in the p-th common electrode group (p is an integer and at least 1 and j is any integer, (2) dividing a unit frame to be displayed into k subfields, and (3) applying a relatively high discharge voltage to the electrode lines of the p-th common electrode group in the p-th subfield, among respective subfields

Abstract: A method for displaying gray levels in a PDP by generating gray data corresponding to externally input image signals and displaying the gray data on the PDP is disclosed. The method comprises generating reference signals based on the image signals, determining a spread filter value according to states of the reference signals, applying the spread filter value to the gray data and generating final gray data, and displaying the final gray data on the PDP. The present invention reduces contour noise generated between moving pictures' adjacent grays.

Abstract: An apparatus for driving a three-electrode alternating current (AC) surface discharge plasma display panel (PDP) includes a scanning driver, an address driver, a common driver and a controller. The scanning driver, in which a scanning circuit is combined with a discharge sustaining circuit with respect to each of the scan electrode lines, applies scanning signals to scan electrode lines in response to scan data in a predetermined scanning order during an address period for forming wall charges at pixels to be selected and also applies discharge sustaining signals to scan electrode lines in response to discharge sustain data during a sustain-discharge period for generating light at the selected pixels.

Abstract: Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. By generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.