Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.

Abstract: A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.

Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.

Abstract: An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

Abstract: Proposed is a three-dimensionally stacked multi-mode sensor for simultaneously detecting pressure and temperature. The multi-mode sensor includes a temperature sensor part including a first thin film transistor; and a pressure sensor part including a second thin film transistor and a piezoresistive layer stacked in a perpendicular direction on the temperature sensor part, the piezoresistive layer including a piezoresistive sheet. The multi-mode sensor can accurately detect pressure and temperature simultaneously without being affected by temperature changes.

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.

Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

Abstract: An integrated circuit may include a first function cell and a second function cell each corresponding to a first circuit, wherein the first function cell may include a first pattern extending in a first direction along a first grid in a first layer and a second pattern extending in the first direction along a second grid in a second layer, the first grid may have a first pitch greater than a second pitch of the second grid in a second direction crossing the first direction, and the second function cell may include a layout of the first function cell and have a length greater than a length of the first function cell by the first pitch in the second direction.

Abstract: Integrated circuits including abutted blocks and methods of designing layouts of the integrated circuits are disclosed. The integrated circuit includes a first block having a first function cell array therein, which is at least partially surrounded by a first plurality of finishing cells, and a second block extending adjacent the first block. The second block includes a second function cell array therein, which is at least partially surrounded by a second plurality of finishing cells. The first plurality of finishing cells include: (i) a first finishing cell placed at a boundary of the integrated circuit, and (ii) a second finishing cell different from the first finishing cell, which is placed at a boundary between the first block and the second block.

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.