Patents by Inventor Sanghoon BAEK
Sanghoon BAEK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170271332Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.Type: ApplicationFiled: June 6, 2017Publication date: September 21, 2017Inventors: Panjae PARK, Sutae KIM, Donghyun KIM, Ha-Young KIM, Jung-Ho DO, Sunyoung PARK, Sanghoon BAEK, Jaewan CHOI
-
Patent number: 9704862Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.Type: GrantFiled: September 15, 2015Date of Patent: July 11, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Panjae Park, Sutae Kim, Donghyun Kim, Ha-Young Kim, Jung-Ho Do, Sunyoung Park, Sanghoon Baek, Jaewan Choi
-
Publication number: 20170148687Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.Type: ApplicationFiled: November 14, 2016Publication date: May 25, 2017Inventors: JUNG-HO DO, JONGHOON JUNG, SANGHOON BAEK, SEUNGYOUNG LEE, TAEJOONG SONG, JINYOUNG LIM
-
Publication number: 20170148727Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.Type: ApplicationFiled: November 18, 2016Publication date: May 25, 2017Inventors: JUNG-HO DO, SEUNGYOUNG LEE, JONGHOON JUNG, JINYOUNG LIM, GIYOUNG YANG, SANGHOON BAEK, TAEJOONG SONG
-
Patent number: 9652580Abstract: A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.Type: GrantFiled: May 12, 2015Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Taejoong Song, Jae-Ho Park, Sanghoon Baek, Giyoung Yang, Sang-Kyu Oh, Hyosig Won
-
Patent number: 9646960Abstract: A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.Type: GrantFiled: February 17, 2016Date of Patent: May 9, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sanghoon Baek, Jung-Ho Do, Taejoong Song, Giyoung Yang, Seungyoung Lee, Jinyoung Lim
-
Patent number: 9640444Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.Type: GrantFiled: July 23, 2015Date of Patent: May 2, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Do, Sanghoon Baek, Sang-Kyu Oh, Kwanyoung Chun, Sunyoung Park, Taejoong Song
-
Publication number: 20170110372Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Inventors: SANGHOON BAEK, JAE-HO PARK, SEOLUN YANG, TAEJOONG SONG, SANG-KYU OH
-
Publication number: 20170062403Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.Type: ApplicationFiled: August 17, 2016Publication date: March 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taejoong SONG, Ha-Young KIM, Jung-Ho DO, Sanghoon BAEK, Jinyoung LIM, Kwangok JEONG
-
Publication number: 20170062475Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.Type: ApplicationFiled: September 30, 2016Publication date: March 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taejoong SONG, Ha-Young KIM, Jung-Ho DO, Sanghoon BAEK, Jinyoung LIM, Kwangok JEONG
-
Patent number: 9564368Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.Type: GrantFiled: March 22, 2016Date of Patent: February 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sanghoon Baek, Jae-Ho Park, Seolun Yang, Taejoong Song, Sang-Kyu Oh
-
Publication number: 20170032074Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.Type: ApplicationFiled: June 16, 2016Publication date: February 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: TAEJOONG SONG, SANGHOON BAEK, SUNGWE CHO, JUNG-HO DO, GIYOUNG YANG, JINYOUNG LIM
-
Patent number: 9536946Abstract: A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.Type: GrantFiled: August 24, 2015Date of Patent: January 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Ho Park, Taejoong Song, Sanghoon Baek, Jintae Kim, Giyoung Yang, Hyosig Won
-
Patent number: 9496179Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.Type: GrantFiled: August 24, 2015Date of Patent: November 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Ho Do, Sanghoon Baek, Sunyoung Park, Sang-Kyu Oh, Jintae Kim, Hyosig Won
-
Publication number: 20160300826Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.Type: ApplicationFiled: April 8, 2016Publication date: October 13, 2016Inventors: Seungyoung LEE, Sanghoon BAEK, Jung-Ho DO
-
Patent number: 9449970Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.Type: GrantFiled: August 19, 2015Date of Patent: September 20, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Do, Sanghoon Baek, Sunyoung Park, Moo-Gyu Bae, Taejoong Song
-
Publication number: 20160254256Abstract: A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.Type: ApplicationFiled: February 17, 2016Publication date: September 1, 2016Inventors: SANGHOON BAEK, JUNG-HO DO, TAEJOONG SONG, GIYOUNG YANG, SEUNGYOUNG LEE, JINYOUNG LIM
-
Publication number: 20160204112Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.Type: ApplicationFiled: March 22, 2016Publication date: July 14, 2016Inventors: SANGHOON BAEK, JAE-HO PARK, SEOLUN YANG, TAEJOONG SONG, SANG-KYU OH
-
Patent number: 9335172Abstract: Provided is an apparatus for measuring a location of an underwater vehicle, including a hull information generating unit dividing a hull surface into a plurality of areas, and generating normal vector information for each area and level information which is information for a depth that each area is submerged into water, a vehicle information receiving unit receiving attitude and depth information for a vehicle attached to the hull surface, and a location determining unit comparing the attitude information for the vehicle with the normal vector information for the area, and comparing the depth information for the vehicle and the level information for the area to determine a location of the vehicle.Type: GrantFiled: July 13, 2012Date of Patent: May 10, 2016Assignee: SAMSUNG HEAVY IND. CO., LTDInventors: Jaeyong Lee, Sanghoon Baek, Yunkyu Choi, Youngjun Park, Jongho Eun
-
Patent number: 9324619Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.Type: GrantFiled: July 31, 2015Date of Patent: April 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sanghoon Baek, Jae-Ho Park, Seolun Yang, Taejoong Song, Sang-Kyu Oh