Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a substrate with a first active area and a second active area spaced apart from each other in a first horizontal direction; a plurality of normal cells arranged on a first surface of the substrate; a power wiring structure arranged on a second surface of the substrate; and a power gating cell arranged on the first surface of the substrate. The power gating cell includes: a sleep control transistor arranged in the first active area; and a through via penetrating the second active area of the substrate. The power gating cell is configured to provide a virtual power voltage to the plurality of normal cells through a virtual power line based on a power voltage supplied from the power wiring structure through the through via and a power line.

Abstract: A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.

Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.

Abstract: A semiconductor device includes: a device layer including first and second active patterns, extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction, intersecting the first direction, on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer, and including first and second lower wiring patterns extending in the first direction, located on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer, and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction.

Abstract: An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

Abstract: Provided is an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells, wherein a distance between a pair of second vertical channel structures of a first cell and an adjacent pair of first vertical channel structures in a second cell, all facing a cell boundary between the first and second cells, is the same as a distance between the pair of the first vertical channel structures and a pair of second vertical channel structures arranged next to the pair of the first vertical channel structures in the first cell.

Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.

Abstract: A semiconductor device includes first and second active patterns, a first gate structure, first and second channels, and first and second source/drain layers. The first and second active patterns extend in a first direction, and are spaced apart in a second direction. The first gate structure extends in the second direction on the first and second active patterns. The first channels are spaced apart in a third direction on the first active pattern. The second channels are spaced apart in the third direction on the second active pattern. The first source/drain layer having a first conductivity type is formed at a side of the first gate structure to contact the first channels. The second source/drain layer having a second conductivity type is formed at a side of the first gate structure to contact the second channels. Widths in the second direction of the first and second channels are different.

Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

Abstract: A layout method is provided. The layout method may include placing first and second standard cells from a standard cell library, interconnecting the placed standard cells to generate a layout draft, confirming placement and routing at a boundary region between the interconnected standard cells, and revising the layout draft based on the confirmation. Each of the standard cells includes, in part, a conductive line that extends in the first direction and is interconnected to an adjacent standard cell through a source/drain via. To confirm the placement and routing, a first spaced distance from a tip of one of the conductive lines to a tip of the other conductive line, and a second spaced distance from the tip of the first conductive line to the cell boundary are compared with preset threshold values. Revising the layout draft may include adjusting a tip position of one of the conductive lines.

Abstract: Disclosed is a thin-film transistor-based pressure sensor including a gate electrode; a gate dielectric layer provided on the gate electrode; a semiconductor layer provided on the gate dielectric layer; and a source electrode and a drain electrode provided on the semiconductor layer, wherein each of the source and drain electrodes has an elastic body that includes: an elastic part having a protrusion; and a conductive part provided on a surface of the elastic part and having a conductive material. According to the pressure sensor and a method of manufacturing the same of the present invention, the elastic body coated with the conductive material is patterned to serve as the source electrode and the drain electrode of the pressure sensor whereby it is possible to drive an active matrix, drive the pressure sensor with low power, and manufacture the pressure sensor through a simple process.

Abstract: A semiconductor device includes: a device layer including first and second active patterns, extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction, intersecting the first direction, on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer, and including first and second lower wiring patterns extending in the first direction, located on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer, and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction.