Patents by Inventor Sang-Hoon Cho

Sang-Hoon Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090061615
    Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming an insulation layer over the substrate, forming a photoresist pattern for a contact hole over the insulation layer, wherein the photoresist pattern includes an opening having a critical dimension (CD) greater than a desired contact CD, forming a contact hole by selectively etching the insulation layer using the photoresist pattern, and forming a spacer on a sidewall of the contact hole until a CD of the contact hole whose sidewall is covered by the spacer is reduced to a desired contact CD.
    Type: Application
    Filed: December 26, 2007
    Publication date: March 5, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sang-Hoon CHO, Sang-Oh LEE
  • Publication number: 20090045518
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of conductive patterns over a substrate, forming a spin on dielectric (SOD) layer filling a portion of space between the conductive patterns, and forming an insulation pattern filling the remaining space over the SOD layer, wherein the stacked structure of the SOD layer and the insulation pattern forms a first interlayer dielectric layer.
    Type: Application
    Filed: June 30, 2008
    Publication date: February 19, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventor: Sang-Hoon CHO
  • Publication number: 20080132051
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of bulb-shaped recesses in a substrate, forming a gate insulation layer over the substrate including the bulb-shaped recesses, forming a patterned first conductive layer over sidewalls of a bulb pattern of the corresponding bulb-shaped recesses, and forming a patterned second conductive layer over the gate insulation layer while filling the bulb-shaped recesses.
    Type: Application
    Filed: May 11, 2007
    Publication date: June 5, 2008
    Inventor: Sang-Hoon Cho
  • Publication number: 20080102639
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 1, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Yong-Tae CHO, Suk-Ki KIM, Sang-Hoon CHO
  • Publication number: 20070072411
    Abstract: A method for forming a metal line in a semiconductor device includes forming a plug buried in an inter-layer insulation layer formed over a substrate, forming a metal line layer over the plug and the substrate, forming a contact mask over the metal line layer, etching first portions of the metal line layer using the contact mask as an etch mask to form openings, forming a spacer layer over the metal line layer and the contact mask, and etching second portions of the metal line layer underneath the openings until portions of the inter-layer insulation layer are exposed to form spacers on sidewalls of the first portions of the metal line layer and the contact mask and to obtain isolated metal lines.
    Type: Application
    Filed: June 8, 2006
    Publication date: March 29, 2007
    Inventors: Sang-Hoon Cho, Ik-Soo Choi
  • Publication number: 20070004194
    Abstract: A method for fabricating a semiconductor device with a deep opening is provided. The method includes: forming an insulation layer on a substrate; selectively etching the insulation layer to form first openings; enlarging areas of the first openings; forming anti-bowing spacers on sidewalls of the enlarged first openings; and etching portions of the insulation layer remaining beneath the enlarged first openings to form second openings.
    Type: Application
    Filed: December 30, 2005
    Publication date: January 4, 2007
    Inventors: Yong-Tae Cho, Hae-Jung Lee, Sang-Hoon Cho
  • Publication number: 20060246708
    Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
    Type: Application
    Filed: December 30, 2005
    Publication date: November 2, 2006
    Inventors: Hae-Jung Lee, Sang-Hoon Cho, Suk-Ki Kim