Patents by Inventor Sang-Hyun Sung

Sang-Hyun Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11373701
    Abstract: A semiconductor device includes a first wafer including a row decoder region in which a plurality of pass transistors are arranged in a row direction and a column direction; a plurality of first bonding pads, respectively coupled to the plurality of pass transistors that are disposed in a plurality of rows on one surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in a different row from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Sung, Sung Lae Oh, Je Hyun Choi
  • Publication number: 20220189875
    Abstract: A three-dimensional memory device includes a plurality of electrode stacks stacked on a substrate in a vertical direction, each of the plurality of electrode stacks including a plurality of interlayer dielectric layers alternately stacked in the vertical direction with a plurality of electrode layers; and a plurality of staircase structures defined in the plurality of electrode stacks, each of the plurality of staircase structures configured by pad regions of electrode layers in an electrode stack that are disposed in a staircase shape, a staircase structure of an electrode stack lower in the plurality of electrode stacks has a larger width than a staircase structure of an electrode stack that is higher in the plurality of electrode stacks.
    Type: Application
    Filed: April 27, 2021
    Publication date: June 16, 2022
    Inventors: Sang Hyun SUNG, Sung Lae OH
  • Patent number: 11355066
    Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: June 7, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dae Sik Lee, Si Duk Sung, Sang Hyun Lee
  • Patent number: 11349159
    Abstract: Provided are a battery management system and a battery pack including the same. The battery management system includes a plurality of slave controllers, a plurality of temperature sensors, and a master controller. The plurality of temperature sensors are disposed in a plurality of different regions within the battery pack in a distributed fashion. The master controller is communicably coupled to the plurality of temperature sensors through a wired communication network. The master controller is communicably coupled to the plurality of slave controllers through a wireless communication network. The master controller determines a position of each of the plurality of slave controllers based on a temperature value of each region measured by the plurality of temperature sensors.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 31, 2022
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Ji-Won Hwang, Yean-Sik Choi, Ji-Eun Kim, Chang-Hyun Sung, Sang-Hoon Lee
  • Patent number: 11342009
    Abstract: A device and a method for equalizing and precharging a cell module, which may form a circuit for performing a corresponding operation by a converter unit by selectively connecting the converter unit and one or more cell modules by controlling a conduction state of a switching unit based on an operation which the converter intends to perform.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 24, 2022
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Chang Hyun Sung, Sang Hoon Lee, Yean Sik Choi
  • Publication number: 20220149321
    Abstract: A display device and a manufacturing method thereof, and a display device including: a substrate including a display area, an opening area positioned in the display area, and a peripheral area positioned between the opening area and the display area; a transistor positioned in the display area of the substrate; a first electrode connected to the transistor; a second electrode positioned on the first electrode; an inorganic pattern portion positioned in the peripheral area of the substrate; and an intermediate layer positioned between the first electrode and the second electrode, and including at least one organic layer positioned on the inorganic pattern portion. The inorganic pattern portion includes a plurality of inorganic patterns spaced apart from each other.
    Type: Application
    Filed: June 1, 2021
    Publication date: May 12, 2022
    Inventors: Woo Sik JEON, Sang Yeol KIM, Tae Hyun SUNG, Seung Soo HONG, Eon Seok OH
  • Publication number: 20220139449
    Abstract: A semiconductor device includes a first wafer including a row decoder region in which a plurality of pass transistors are arranged in a row direction and a column direction; a plurality of first bonding pads, respectively coupled to the plurality of pass transistors that are disposed in a plurality of rows on one surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in a different row from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.
    Type: Application
    Filed: February 9, 2021
    Publication date: May 5, 2022
    Inventors: Sang Hyun SUNG, Sung Lae OH, Je Hyun CHOI
  • Patent number: 11315914
    Abstract: A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Sung, Young Ki Kim, Jin Ho Kim, Byung Hyun Jun
  • Patent number: 11282819
    Abstract: A semiconductor device includes a first chip, divided into a plurality of regions, including a plurality of first pads and a plurality of first test pads in each of the plurality of regions; and a second chip including a plurality of second pads corresponding to the plurality of first pads and a plurality of second test pads corresponding to the plurality of first test pads, and bonded onto the first chip such that the plurality of second pads are coupled to the plurality of first pads. The second chip includes a voltage generation circuit linked to the plurality of second pads, that provides a compensated voltage to the plurality of second pads for each of the plurality of regions, based on a voltage drop value for each region due to a contact resistance between the plurality of first test pads and the plurality of second test pads.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: March 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Sang Hyun Sung, Kwang Hwi Park, Je Hyun Choi
  • Publication number: 20220077172
    Abstract: A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers.
    Type: Application
    Filed: February 2, 2021
    Publication date: March 10, 2022
    Inventors: Jin Ho KIM, Young Ki KIM, Sang Hyun SUNG, Sung Lae OH, Byung Hyun JEON
  • Publication number: 20220020764
    Abstract: A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.
    Type: Application
    Filed: January 8, 2021
    Publication date: January 20, 2022
    Inventors: Sung Lae OH, Jin Ho KIM, Sang Woo PARK, Sang Hyun SUNG
  • Publication number: 20220005820
    Abstract: A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.
    Type: Application
    Filed: January 8, 2021
    Publication date: January 6, 2022
    Inventors: Jin Ho KIM, Kwang Hwi PARK, Sang Hyun SUNG, Sung Lae OH, Chang Woon CHOI
  • Patent number: 11195852
    Abstract: A semiconductor memory device includes a substrate having a second region extending in a first direction; a memory block including electrodes; a slit dividing the memory block into first and second electrode structures in the second region; and step-shaped grooves formed in the memory block in the second region, and divided by the slit. In the second region, the first and second electrode structures are adjacently disposed with the slit interposed therebetween, in a second direction intersecting with the first direction. Each of the electrodes of the first electrode structure has a first pad region, each of the electrodes of the second electrode structure has a second pad region, and first and second pad regions of the first and second electrode structures which are positioned in the same step-shaped groove and are disposed at the same layers are adjacently disposed in the second direction with the slit interposed therebetween.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Jin Ho Kim, Sang Hyun Sung, Young Ki Kim, Byung Hyun Jeon
  • Publication number: 20210366919
    Abstract: A three-dimensional memory device includes an electrode structure including a plurality of interlayer dielectric layers and a plurality of electrode layers which are alternately stacked on a first substrate, each of the plurality of electrode layers having a pad part which does not overlap with another electrode layer positioned on the electrode layer; a pass transistor positioned below the first substrate; and a first contact passing through the electrode structure from the pad part of one of the plurality of electrode layers, and coupling the pad part and the pass transistor.
    Type: Application
    Filed: September 8, 2020
    Publication date: November 25, 2021
    Inventors: Sang Hyun SUNG, Jin Ho KIM, Sung Lae OH
  • Publication number: 20210272631
    Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first substrate layer including a logic circuit, and a plurality of second substrate layers stacked on the first substrate layer, the plurality of second substrate layers including a memory cell array. Each of the plurality of second substrate layers includes, a transfer circuit, coupled to a row line of the memory cell array, that is disposed over the second substrate layer and selectively coupled to a global row line.
    Type: Application
    Filed: September 23, 2020
    Publication date: September 2, 2021
    Inventors: Jin Ho KIM, Sang Hyun SUNG, Sung Lae OH
  • Publication number: 20210242175
    Abstract: A semiconductor memory device includes a plurality of first pads disposed in one surface of a memory chip which includes a memory cell array and a plurality of row lines coupled to the memory cell array, and coupled to the row lines, respectively; and a plurality of second pads disposed in one surface of a circuit chip which is boned to the one surface of the memory chip, coupled to pass transistors, respectively, of the circuit chip, and bonded to the first pads, respectively. The second pads are aligned with the pass transistors, with the same pitch as a pitch of the pass transistors.
    Type: Application
    Filed: June 19, 2020
    Publication date: August 5, 2021
    Inventors: Jin Ho KIM, Young Ki KIM, Sang Hyun SUNG, Sung Lae OH, Byung Hyun JUN
  • Publication number: 20210210475
    Abstract: A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.
    Type: Application
    Filed: June 2, 2020
    Publication date: July 8, 2021
    Inventors: Sang Hyun SUNG, Young Ki KIM, Jin Ho KIM, Byung Hyun JUN
  • Publication number: 20210098424
    Abstract: A semiconductor device includes a first chip, divided into a plurality of regions, including a plurality of first pads and a plurality of first test pads in each of the plurality of regions; and a second chip including a plurality of second pads corresponding to the plurality of first pads and a plurality of second test pads corresponding to the plurality of first test pads, and bonded onto the first chip such that the plurality of second pads are coupled to the plurality of first pads. The second chip includes a voltage generation circuit linked to the plurality of second pads, that provides a compensated voltage to the plurality of second pads for each of the plurality of regions, based on a voltage drop value for each region due to a contact resistance between the plurality of first test pads and the plurality of second test pads.
    Type: Application
    Filed: March 25, 2020
    Publication date: April 1, 2021
    Inventors: Sung Lae OH, Sang Hyun SUNG, Kwang Hwi PARK, Je Hyun CHOI
  • Patent number: 10923495
    Abstract: A semiconductor memory device includes a substrate including a cell region and a slimming region; a logic structure disposed over the substrate, the logic structure including logic circuit elements and bottom wiring lines electrically coupled to the logic circuit elements; a source plate disposed over the logic structure; a memory structure including a plurality of memory cells and a plurality of gate electrode layers, wherein the plurality of memory cells are disposed over the source plate of the cell region and a plurality of gate electrode layers are stacked over the source plate of the cell region and the slimming region to be separated from one another and are coupled to the plurality of memory cells; and a first slit cutting the source plate at a boundary between the cell region and the slimming region, wherein the source plate of the slimming region is floated regardless an operation of the memory cells and the logic circuit elements.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Jin-Ho Kim, Young-Ki Kim, Jeong-Hwan Kim, Sang-Hyun Sung
  • Publication number: 20210036007
    Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.
    Type: Application
    Filed: February 1, 2020
    Publication date: February 4, 2021
    Inventors: Sung Lae OH, Jin Ho KIM, Sang Woo PARK, Sang Hyun SUNG, Soo Nam JUNG, Chang Woon CHOI