Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

Abstract: A display device includes: a display panel; a driving voltage generator; a power voltage generator; an input voltage generator; and a timing controller. The display panel is provided with a pixel configured to emit light by using a driving voltage. The driving voltage generator is configured to supply the driving voltage to the pixel. The power voltage generator is configured to generate power voltages for driving of the display panel by using an input voltage, and generating an input voltage sensing value by sensing the input voltage. The input voltage generator is configured to supply the input voltage to the power voltage generator. The timing controller is configured to control an operation of at least one of the driving voltage generator, the power voltage generator, and the input voltage generator according to the input voltage sensing value.

Abstract: A secondary battery activation device capable of effectively removing gas generated inside a secondary battery cell during an activation process of a secondary battery and a secondary battery manufacturing method using the same are provided. The secondary battery activation device includes a first pressing unit comprising a first pressing plate and a plurality of first elastic pressing members located on a first surface of the first pressing plate, and a second pressing unit comprising a second pressing plate and a plurality of second elastic pressing members located on a second surface of the second pressing plate, the second surface of the second pressing plate being arranged to face the first surface of the first pressing plate.

Abstract: Disclosed is a neuromorphic memory element, which includes a first electrode; a second electrode; a first thin film layer adjacent to the first electrode between the first electrode and the second electrode and that is configured to emulate a neuronal plasticity by performing a volatile storage function based on a voltage difference between the first electrode and the second electrode; and a second thin film layer between the first thin film layer and the second electrode and that is configured to emulate a synaptic plasticity by performing a non-volatile storage function.

Abstract: A memory device includes a first semiconductor structure including pass transistors defined in a row decoder region of a substrate, a first bonding layer including first bonding pads, and bottom wiring layers disposed between the substrate and the first bonding layer; a second semiconductor structure including a second bonding layer including second bonding pads bonded to the first bonding pads, a memory cell array, and a top wiring layer disposed between the second bonding layer and the memory cell array; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the bottom wiring layers include bottom wiring layers of a first tier and bottom wiring layers of a second tier disposed over the bottom wiring layers of the first tier, and the global lines are disposed in at least one of the bottom wiring layers of the first tier.

Abstract: A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

Abstract: A semiconductor memory device includes a memory cell array disposed over a substrate extending in a first direction and a second direction intersecting with the first direction in a first semiconductor layer, and including a plurality of cell units and at least two via regions that are arranged in the second direction, wherein a width of each of the at least two via regions in the second direction is a multiple of a width of each of the plurality of cell units in the second direction.

Abstract: A memory device includes a pass transistor circuit included in a first wafer, and configured to transfer an operating voltage to row lines of a memory cell array; and a discharge transistor circuit included in a second wafer that overlaps with the first wafer in a vertical direction, and configured to transfer a discharge voltage to at least one of the row lines.

Abstract: A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers.

Abstract: A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.

Abstract: A three-dimensional memory device includes a plurality of electrode stacks stacked on a substrate in a vertical direction, each of the plurality of electrode stacks including a plurality of interlayer dielectric layers alternately stacked in the vertical direction with a plurality of electrode layers; and a plurality of staircase structures defined in the plurality of electrode stacks, each of the plurality of staircase structures configured by pad regions of electrode layers in an electrode stack that are disposed in a staircase shape, a staircase structure of an electrode stack lower in the plurality of electrode stacks has a larger width than a staircase structure of an electrode stack that is higher in the plurality of electrode stacks.

Abstract: A memory device may include an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked on a substrate; a trench in the electrode structure, and having an upper sidewall, a lower sidewall and a horizontal portion that couples the upper sidewall to the lower sidewall and that is parallel to a top surface of the substrate; a dielectric layer in the trench; and a slimming hole in the electrode structure having a sidewall of the trench and a region of the dielectric layer, and having a bottom surface disposed on an electrode layer on which the horizontal portion of the trench is positioned.

Abstract: A three-dimensional memory device includes a first electrode structure and a second electrode structure extending in a first direction, being adjacent to each other in a second direction intersecting with the first direction, and each including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate; a plurality of first slimming holes formed in the first electrode structure to expose pad regions of the electrode layers of the first electrode structure, and arranged in the first direction; and a plurality of second slimming holes formed in the second electrode structure to expose pad regions of the electrode layers of the second electrode structure, and arranged in the first direction, wherein a first slimming hole and a second slimming hole which are adjacent in the second direction have different depths.

Abstract: A memory device includes a memory cell array included in a first semiconductor layer, and including a plurality of row lines that extend in a first direction, each of the plurality of row lines having a pad part disposed in a slimming region; a row decoder included in a second semiconductor layer disposed under the first semiconductor layer, and overlapping the memory cell array in a vertical direction; slimming regions disposed on both sides of the row decoder in the first direction; and a plurality of wiring lines coupling the pad parts of the plurality of row lines and the row decoder.

Abstract: A semiconductor memory device includes a first semiconductor layer including a memory cell array; a second semiconductor layer including a first substrate and a page buffer circuit which is configured on the first substrate; a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer in a vertical direction, and including a second substrate and a second logic circuit which is configured on an element region of the second substrate; and a first contact plug passing through a coupling region of the second substrate which overlaps the page buffer circuit in the vertical direction.

Abstract: A semiconductor memory device includes a memory structure including a plurality of memory cells which are disposed on a cell region of a source plate; a plurality of contact plugs passing through the source plate in a coupling region of the source plate including at least a portion of a center portion of the source plate, and separated from the source plate by a dielectric layer pattern; a discharge contact passing through the source plate in the coupling region, and coupled to the center portion of the source plate; and a discharge region coupled to the discharge contact. The discharge region is located in a substrate below the source plate.

Abstract: A three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; and a plurality of through holes passing through the electrode structure in a vertical direction, and including pad regions at the transition between portions of the through holes have different widths.

Abstract: A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction; and a cell region including a plane which is coupled to the plurality of bit lines, wherein the plane is divided into a plurality of memory groups each including a plurality of partial pages to be disposed in a plurality of rows in the first direction.

Abstract: A memory device includes a pass transistor circuit included in a first wafer, and configured to transfer an operating voltage to row lines of a memory cell array; and a discharge transistor circuit included in a second wafer that overlaps with the first wafer in a vertical direction, and configured to transfer a discharge voltage to at least one of the row lines.

Abstract: A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.