Abstract: A semiconductor memory device having a driver configured to sequentially perform over-driving and normal driving operations is presented. The semiconductor memory device includes a driver that outputs a drive signal, that over-drives the drive signal with an over-drive voltage having a voltage level higher than a normal drive voltage, and then subsequently normally drives the drive signal with the normal drive voltage. The semiconductor memory device also includes a drive voltage adjuster that detects a level of the over-drive voltage and compensates for a change in the voltage level of the normal drive voltage in response to the detected level of the over-drive voltage.

Abstract: An internal voltage generator of a semiconductor memory device generates an internal voltage sensitive to a change in a temperature. The internal voltage generator includes a reference voltage generator, an internal voltage detecting unit and an internal voltage pumping unit. The reference voltage generator generates a reference voltage which is inversely proportional to the change in the temperature. The internal voltage detecting unit detects a difference between the reference voltage and the internal voltage to output a pumping control signal according to a detecting result, wherein the pumping control signal has an identical temperature characteristic as the reference voltage. The internal voltage pumping unit generates the internal voltage by a pumping operation in response to the pumping control signal.

Abstract: An internal voltage generator of a semiconductor device includes a charge pumping unit for performing a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit for performing a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant independent of a temperature change in a second temperature range to generate the internal voltage.

Abstract: There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage.

Abstract: An internal voltage generator of a semiconductor integrated circuit includes a first driver that outputs an internal voltage by using an internal reference voltage during an active operation in accordance with a detection signal generated by using an external voltage and an active enable signal activated during an activation mode, and a second driver that outputs an internal voltage by using the internal reference voltage during the active operation in accordance with the active enable signal.

Abstract: A buffer circuit of a semiconductor memory apparatus includes a compensation voltage generation unit configured to generate a compensation voltage in response to a level of a reference voltage; and a buffering unit configured to generate an output signal by buffering an input signal depending on the reference voltage and control a transition section of the output signal depending on a level of the compensation voltage.

Abstract: A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal.

Abstract: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.

Abstract: A buffer of a semiconductor memory apparatus includes a buffering section configured to generate an output signal by buffering an input signal. A mismatch compensation section generates a control voltage in correspondence with sizes of a second transistor of the same type as a first transistor constituting the buffering section, wherein the buffering section controls a transition time of the output signal in response to a level of the control voltage.

Abstract: A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command.

Abstract: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.

Abstract: An internal voltage generator stably supplies an internal voltage in a semiconductor device. The internal voltage generator includes: a first internal voltage generating means for supplying a first internal voltage which has a level corresponding to a first reference voltage using an external voltage; a second internal voltage generating means for supplying a second internal voltage which has a level corresponding to a second reference voltage using the external voltage; and a third internal voltage generating means for supplying a third internal voltage which has a level corresponding to a third reference voltage generated based on the first internal voltage, using the second internal voltage as a power source.

Abstract: An internal voltage generator includes: an internal voltage driving unit for supplying an internal voltage corresponding to a reference voltage maintaining a predetermined voltage level regardless of a temperature variation; and a temperature compensation current sinking unit for sinking a current generated by an internal voltage in response to a voltage level inversely proportional to a temperature.

Abstract: An active driver includes an internal voltage supply node, an internal voltage generator, and a test internal voltage driving circuit. The internal voltage generator generates an internal voltage having a first potential level in a normal operation to provide the internal voltage to the internal voltage supply node. The test internal voltage driving circuit drives an external voltage having a second potential level higher than the first potential level to the internal voltage supply node in a test operation.

Abstract: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.

Abstract: An internal voltage generator for use in a semiconductor memory device includes a first voltage detection unit, a second voltage detection unit, a detection signal generation unit, and an internal voltage generation unit. The first voltage detection unit detects a voltage level of an internal voltage changing linearly depending on a temperature variation to output a first detection signal. The second voltage detection unit detects the voltage level having a constant value without concerning the temperature variation to output a second detection signal. The detection signal output unit combines the first and the second detection signal to generate a combined detection signal for detecting the voltage level linearly varying according to the temperature variation in a first range of temperature and detecting the voltage level having the constant value in a second range of temperature.

Abstract: A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node connected to an external resistor and a reference voltage to generate pull-up calibration codes. The calibration circuit also includes a pull-up calibration resistor unit configured to pull up the calibration node in response to the pull-up calibration codes. The pull-up calibration resistor unit is calibrated such that its resistance becomes higher as a power supply voltage increases.

Abstract: An inter voltage generation circuit includes a pumping voltage generator to generate a pumping voltage, a level comparator to compare the pumping voltage level with a peripheral voltage level and output an enable signal depending on the comparison result, and a peripheral voltage generator to output a pumping enable signal according to the enable signal and generate a peripheral voltage according to the enable signal.

Abstract: An internal voltage generation circuit of a semiconductor memory device controls a dead zone voltage, in which the driving unit that supplies a power supply voltage, does not need to operate. An internal voltage having a dead zone is determined by first and second driving signals based on a level of a reference voltage, and by selectively supplying first and second voltages by means of the first and second driving signals.

Abstract: Bandgap reference voltage generation circuit in semiconductor memory device includes a first current generator configured to generate a first current proportional to a change of a temperature by using temperature characteristic of a diode-connected MOS transistor, a second current generator configured to generate a second current inversely proportional to the change of the temperature by using the temperature characteristic of a diode-connected MOS transistor and a summation unit configured to mirror and sum the output currents of the first current generator and the second current generator, and output a reference voltage.