Abstract: A coil component may include a body including a plurality of insulating layers having coil patterns disposed on the plurality of insulating layers. The coil pattern may include a coil portion, a leading portion disposed on one side of the insulating layer, and a connection portion connecting the coil portion and the leading portion, a pattern line of the coil portion may have an arc shape, and the connection portion may be formed in a tangent line direction of the coil portion from one end of the leading portion.

Abstract: An inductor includes a body including a coil and a dummy electrode, spaced apart from the coil, and having a first side surface and a second side surface disposed to oppose each other in a first direction, a top surface and a bottom surface disposed to oppose each other in a second direction, and a first end surface and a second end surface disposed to oppose each other in a third direction, and external electrodes including a first external electrode, disposed on an external surface of the body, extending from the first end surface to a portion of the bottom surface and a second external electrode, disposed on an external surface of the body, extending from the second end surface to a portion of the bottom surface.

Abstract: A method of manufacturing a coil device and the coil device includes a base layer and a coil pattern formed on a surface of the base layer. The method of manufacturing a coil device includes forming a seed layer of a coil by bonding a copper foil to a base layer, etching to remove a portion of the copper foil, and plating a plating layer on the seed layer.

Abstract: An antenna module includes an antenna substrate including a core layer, insulating layers disposed on opposite surfaces of the core layer, and wiring layers including antenna patterns. The antenna substrate has first and second recess portions. The antenna module further includes a passive component disposed in the first recess portion, a semiconductor chip disposed in the second recess portion and having an active surface, an encapsulant encapsulating at least portions of the semiconductor chip and the passive component, and a connection portion disposed on the active surface of the semiconductor chip and including redistribution layers electrically connected to the semiconductor chip. The passive component has a thickness greater than that of the semiconductor chip, and the first recess portion has a depth greater than that of the second recess portion.

Abstract: An inductor includes a body including a plurality of insulating layers and a plurality of coil patterns are disposed on each of the plurality of insulating layers, and first and second external electrodes disposed on an external surface of the body. The plurality of coil patterns are connected to each other by coil connecting portions and both end portions thereof are electrically connected to the first and second external electrodes through coil lead portions, respectively, to form a coil. The plurality of coil patterns include coil patterns disposed on an outer portion of the body and coil patterns disposed on an inner portion of the body, the coil patterns disposed on the inner portion of the body include first coil patterns electrically connected in parallel, and at least one of the first coil patterns includes an internal side portion having a shape different from shapes of remaining coil patterns.

Abstract: A camera module includes a housing including a lens module; a diaphragm module to form N apertures of different sizes, where N is a natural number, with blades disposed on an object side of the lens module; and a diaphragm driving unit disposed with the diaphragm module, and including a driving coil and a magnetic member disposed opposite to the driving coil, the magnetic member being movable in a direction perpendicular to an optical axis to be fixed in N positions along a movement path.

Abstract: A semiconductor package includes: a frame having first and second through-holes spaced apart from each other; passive components disposed in the first through-hole; a semiconductor chip disposed in the second through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; a first encapsulant covering at least portions of the passive components and filling at least portions of the first through-hole; a second encapsulant covering at least portions of the semiconductor chip and filling at least portions of the second through-hole; and a connection structure disposed on the frame, the passive components, and the active surface of the semiconductor chip and including wiring layers electrically connected to the passive components and the connection pads of the semiconductor chip. The second encapsulant has a higher electromagnetic wave absorption rate than that of the first encapsulant.

Abstract: A coil component includes a body including a plurality of first and second coil patterns, which are alternately disposed, and insulating layers disposed therebetween. The first coil patterns may be connected to the second coil patterns adjacent to the first coil patterns by vias, a plurality of coils including at least one each of the first and second coil patterns may be formed, and the plurality of coils may be connected in parallel to each other.

Abstract: An inductor includes a body in which a plurality of insulating layers on which a plurality of coil patterns are arranged are stacked, and first and second external electrodes disposed on an external surface of the body, wherein the plurality of coil patterns are connected through coil connecting portions and include coil patterns disposed on an outer side and coil patterns disposed on an inner side thereof, a coil pattern disposed on the inner side adjacent to the coil pattern disposed on the outer side includes two coil connecting portions spaced apart from each other and facing each other in a length direction of the body, and a dummy electrode pattern is further disposed in a void portion between two coil connecting portions.

Abstract: A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic wave shielding layer disposed on the semiconductor chip and including a plurality of degassing holes. The electromagnetic wave shielding layer includes a first region and a second region in which densities of the degassing holes are different from each other, the first region having a density of the degassing holes higher than a density of the degassing holes in the second region.

Abstract: A coil component includes: a body having a first surface and a second surface opposing each other in one direction and including a core extending in the one direction; a coil portion embedded in the body and having at least one turn around the core; and an external electrode disposed at least on the first surface of the body and connected to the coil portion. A first distance from the coil portion to a third surface of the body is greater than a second distance from the coil portion to a fourth surface of the body. The third and fourth surfaces oppose each other and have the core disposed therebetween. Turns of the coil portion disposed between the third surface of the body and the core are more than those of the coil portion disposed between the fourth of the body and the core.

Abstract: A coil component includes: a body; a coil part including a coil pattern embedded in the body and having at least one turn winding around on one direction; first and second external electrodes disposed on a surface of the body and connected to the coil part; and a shielding via having a permeability higher than that of the body and extending along the one direction in the body.

Abstract: A thin film capacitor includes: a body formed by alternately stacking first and second electrode layers, with dielectric layers therebetween on a substrate. A plurality of first vias are disposed in the body and electrically connected to the first electrode layers. A plurality of second vias are disposed in the body, electrically connected to the second electrode layers, and disposed alternately with the first vias. A first connection electrode is disposed on an upper surface of the body and connected to the plurality of first vias, a second connection electrode is disposed on the upper surface of the body and connected to the plurality of second vias, and first and second electrode pads are disposed on the first and second connection electrodes, respectively, and formed to not overlap the plurality of first and second vias.

Abstract: A semiconductor package includes a first semiconductor package including a core member having a through-hole, a first semiconductor chip disposed in the through-hole and having an active surface with a connection pad disposed thereon, a first encapsulant for encapsulating at least a portion of the first semiconductor chip, and a connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, a second semiconductor package disposed on the first semiconductor package and including a wiring substrate electrically connected to the connection member, at least one second semiconductor chip disposed on the wiring substrate, and a second encapsulant for encapsulating at least a portion of the second semiconductor chip, and a heat dissipation member covering a lateral surface of the second semiconductor package and exposing an upper surface of the second encapsulant.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween, and first and second external electrodes disposed on one surface of the body and respectively connected to the first and second internal electrodes. The first internal electrode includes a first main portion and a first lead out portion connecting the first main portion and the first external electrode, the second internal electrode includes a second main portion and a second lead out portion connecting the second main portion and the second external electrode, and the second main portion has a greater area than the first main portion and includes a corner portion defining an open space to compensate for a capacitance formed by an area in which the first lead out portion and the second main portion overlap each other.

Abstract: A coil component includes: a body having a first surface and a second surface opposing each other in a thickness direction of the body and a wall surface connecting the first and second surfaces; a coil part including coil patterns and including at least one turn centered on the thickness direction; external electrodes disposed on the first surface of the body and electrically connected to the coil part; a shielding layer including a cap portion disposed on the second surface of the body and side wall portions disposed on the wall surface of the body and each having a first end connected to the cap portion; an insulating layer disposed between the body and the shielding layer; and a gap portion bounded by a second end of the shielding layer opposing the first end and the first surface of the body to expose portions of the wall surface.

Abstract: A chip antenna includes a radiation portion having a block shape and a first surface and a second surface opposing each other, and configured to receive and radiate a feed signal as an electromagnetic wave; a first block made of a dielectric material and coupled to the first surface of the radiation portion; a second block made of a dielectric material and coupled to the second surface of the radiation portion; a ground portion having a block shape and coupled to the first block, and configured to reflect the electromagnetic wave radiated by the radiation portion back toward the radiation portion; and a director having a block shape and coupled to the second block, wherein an overall width of the ground portion, the first block, and the radiation portion is 2 mm or less, and the first block has a dielectric constant of 3.5 or more to 25 or less.

Abstract: A thin-film capacitor includes a body in which a plurality of dielectric layers and first and second electrode layers are alternately stacked on a substrate, first and second electrode pads are on external surfaces of the body, and a plurality of vias are within the body. Among the plurality of vias, a first via connects the first electrode layer and the first electrode pad, and a second via connects the second electrode layer and the second electrode pad. The first via and the second via are units each include a plurality of vias, and the first via unit and the second via unit are alternately disposed on an upper surface of the body.

Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.

Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.