Patents by Inventor Sang-Joon Hwang
Sang-Joon Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11169711Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: GrantFiled: July 29, 2019Date of Patent: November 9, 2021Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&D FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATIONInventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang
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Publication number: 20190354292Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: ApplicationFiled: July 29, 2019Publication date: November 21, 2019Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATIONInventors: Seong-Il O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG
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Patent number: 10416896Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: GrantFiled: May 23, 2017Date of Patent: September 17, 2019Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation, Wisconsin Alumni Research FoundationInventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang
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Patent number: 10347355Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: GrantFiled: October 27, 2017Date of Patent: July 9, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
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Publication number: 20180107406Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: ApplicationFiled: May 23, 2017Publication date: April 19, 2018Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMIN RESEARCH FOUNDATIONInventors: SEONG-IL O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG
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Publication number: 20180068742Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
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Patent number: 9858981Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.Type: GrantFiled: December 8, 2016Date of Patent: January 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Young Lee, Kyo-Min Sohn, Sang-Joon Hwang, Sung-Min Seo, Sang-Bo Lee, Nak-Won Heo
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Patent number: 9831003Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: GrantFiled: April 27, 2017Date of Patent: November 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
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Publication number: 20170229192Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: ApplicationFiled: April 27, 2017Publication date: August 10, 2017Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
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Patent number: 9659669Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: GrantFiled: April 28, 2015Date of Patent: May 23, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
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Publication number: 20170092349Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.Type: ApplicationFiled: December 8, 2016Publication date: March 30, 2017Inventors: Yun-Young Lee, Kyo-Min SOHN, Sang-Joon HWANG, Sung-Min SEO, Sang-Bo LEE, Nak-Won HEO
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Patent number: 9524770Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.Type: GrantFiled: April 29, 2016Date of Patent: December 20, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Young Lee, Kyo-Min Sohn, Sang-Joon Hwang, Sung-Min Seo, Sang-Bo Lee, Nak-Won Heo
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Patent number: 9460766Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.Type: GrantFiled: July 16, 2015Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Yoon Lee, Myeong-O Kim, Kyo-Min Sohn, Sang-Joon Hwang
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Publication number: 20160247553Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.Type: ApplicationFiled: April 29, 2016Publication date: August 25, 2016Inventors: Yun-Young LEE, Kyo-Min SOHN, Sang-Joon HWANG, Sung-Min SEO, Sang-Bo LEE, Nak-Won HEO
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Patent number: 9336906Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.Type: GrantFiled: October 1, 2014Date of Patent: May 10, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Young Lee, Kyo-Min Sohn, Sang-Joon Hwang, Sung-Min Seo, Sang-Bo Lee, Nak-Won Heo
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Patent number: 9298612Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.Type: GrantFiled: August 30, 2013Date of Patent: March 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung Shin, Sang-Joon Hwang, Seung-Man Shin, In-Su Choi, Jung-Ho Jung
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Publication number: 20160071561Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.Type: ApplicationFiled: July 16, 2015Publication date: March 10, 2016Inventors: Tae-Yoon LEE, Myeong-O KIM, Kyo-Min SOHN, Sang-Joon HWANG
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Patent number: 9171605Abstract: Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.Type: GrantFiled: December 11, 2013Date of Patent: October 27, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Sik Kim, Won-Il Bae, Myeong-O Kim, Min-Soo Kim, Ho-Seok Seol, Min-Sang Park, Kyo-Min Sohn, Chi-Hwan Lee, Sang-Joon Hwang
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Patent number: 9165673Abstract: A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.Type: GrantFiled: March 12, 2013Date of Patent: October 20, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Je-Min Yu, Ho-Young Song, Sung-Min Seo, Sang-Joon Hwang
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Publication number: 20150243374Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.Type: ApplicationFiled: April 28, 2015Publication date: August 27, 2015Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn