Patents by Inventor Sang-Joon Hwang

Sang-Joon Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190362134
    Abstract: A makeup evaluation system according to an embodiment of the present invention includes a mobile terminal for photographing a facial image and transmitting the photographed facial image to a makeup server, and the makeup server for storing makeup score data and, when receiving the facial image from the mobile terminal, detecting at least one face region in the facial image, calculating a makeup score for each of the detected face regions on the basis of the makeup score data, and transmitting the calculated makeup score to the mobile terminal.
    Type: Application
    Filed: February 1, 2018
    Publication date: November 28, 2019
    Applicant: LG HOUSEHOLD & HEALTH CARE LTD.
    Inventors: Sang E KIM, Do Hyuk KWON, Do Sik HWANG, Tae Seong KIM, Doo Hyun PARK, Ki Hun BANG, Tae Joon EO, Yo Han JUN, Se Won HWANG
  • Publication number: 20190354292
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Seong-Il O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG
  • Publication number: 20190347971
    Abstract: An application processor includes a scaling rate calculator that determines a scaling rate of first image data based on stress data that includes pixel degradation information for each pixel; and an image processor that generates second image data by decreasing a maximum grayscale value of the first image data based on the scaling rate, where the first image data is received from an external component.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Inventors: DONG-HAK PYO, CHEOL-HWAN EOM, SANG-MYEON HAN, SUN-JOON HWANG
  • Patent number: 10416896
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: September 17, 2019
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation, Wisconsin Alumni Research Foundation
    Inventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang
  • Patent number: 10360828
    Abstract: An application processor includes a scaling rate calculator that determines a scaling rate of first image data based on stress data that includes pixel degradation information for each pixel; and an image processor that generates second image data by decreasing a maximum grayscale value of the first image data based on the scaling rate, where the first image data is received from an external component.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong-Hak Pyo, Cheol-Hwan Eom, Sang-Myeon Han, Sun-Joon Hwang
  • Patent number: 10347355
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Patent number: 10327106
    Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting higher data rates than a 4th generation (4G) communication system such as long term evolution (LTE). A method for positioning a user equipment (UE) in a wireless communication system includes receiving a reference signal (RS) in a first bandwidth from each of a plurality of anchor nodes scheduled for RS transmission by a network server, determining whether a path overlap has occurred between the UE and the anchor nodes based on symmetry of channel impulse responses of the received RSs, transmitting a bandwidth extension request message to the network server, upon occurrence of a path overlap, receiving an RS in a second bandwidth larger than the first bandwidth from each of the plurality of anchor nodes in response to the transmission of the bandwidth extension request message, and generating information required to position the UE, using the RSs received in the second bandwidth.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Joon Hwang, Hyun-Seok Ryu, Jeong-Ho Park, Peng Xue, Sang-Won Choi
  • Publication number: 20180107406
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Application
    Filed: May 23, 2017
    Publication date: April 19, 2018
    Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMIN RESEARCH FOUNDATION
    Inventors: SEONG-IL O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG
  • Publication number: 20180068742
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Application
    Filed: October 27, 2017
    Publication date: March 8, 2018
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Patent number: 9858981
    Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Young Lee, Kyo-Min Sohn, Sang-Joon Hwang, Sung-Min Seo, Sang-Bo Lee, Nak-Won Heo
  • Patent number: 9831003
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Publication number: 20170229192
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Application
    Filed: April 27, 2017
    Publication date: August 10, 2017
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Patent number: 9659669
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Publication number: 20170092349
    Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
    Type: Application
    Filed: December 8, 2016
    Publication date: March 30, 2017
    Inventors: Yun-Young Lee, Kyo-Min SOHN, Sang-Joon HWANG, Sung-Min SEO, Sang-Bo LEE, Nak-Won HEO
  • Patent number: 9524770
    Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: December 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Young Lee, Kyo-Min Sohn, Sang-Joon Hwang, Sung-Min Seo, Sang-Bo Lee, Nak-Won Heo
  • Patent number: 9460766
    Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: October 4, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Yoon Lee, Myeong-O Kim, Kyo-Min Sohn, Sang-Joon Hwang
  • Publication number: 20160247553
    Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
    Type: Application
    Filed: April 29, 2016
    Publication date: August 25, 2016
    Inventors: Yun-Young LEE, Kyo-Min SOHN, Sang-Joon HWANG, Sung-Min SEO, Sang-Bo LEE, Nak-Won HEO
  • Patent number: 9336906
    Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Young Lee, Kyo-Min Sohn, Sang-Joon Hwang, Sung-Min Seo, Sang-Bo Lee, Nak-Won Heo
  • Patent number: 9298612
    Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung Shin, Sang-Joon Hwang, Seung-Man Shin, In-Su Choi, Jung-Ho Jung
  • Publication number: 20160071561
    Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.
    Type: Application
    Filed: July 16, 2015
    Publication date: March 10, 2016
    Inventors: Tae-Yoon LEE, Myeong-O KIM, Kyo-Min SOHN, Sang-Joon HWANG