Abstract: A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a first power supply voltage and pulls down the output terminal to a second power supply voltage based on an output data signal. The pull-down driver pre-emphasizes an initial stage of a pull-down driving operation of the output terminal based on the output data.

Abstract: We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

Abstract: A synchronous semiconductor memory device includes a data input buffer and a data strobe input buffer. The data strobe input buffer includes an input buffer circuit and a detection circuit. The input buffer circuit is configured to be enabled based on an active signal, and to compare a data strobe signal with a first reference voltage to generate an internal data strobe signal. The detection circuit is configured to be enabled based on the active signal, and to compare the data strobe signal with a second reference voltage to generate a detection signal for enabling the data input buffer.

Abstract: A synchronous semiconductor memory device includes a data input buffer and a data strobe input buffer. The data strobe input buffer includes an input buffer circuit and a detection circuit. The input buffer circuit is configured to be enabled based on an active signal, and to compare a data strobe signal with a first reference voltage to generate an internal data strobe signal. The detection circuit is configured to be enabled based on the active signal, and to compare the data strobe signal with a second reference voltage to generate a detection signal for enabling the data input buffer.

Abstract: A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR2 mode of operation for the DDR DRAM.

Abstract: The semiconductor memory device includes a plurality of first data sense amplifiers and a plurality of second data sense amplifiers. Each first data sense amplifier being a voltage sense amplifier, and each first data sense amplifier associated with data lines of a first type, which lead from bit line sense amplifiers. Each second data sense amplifier including a current sense amplifier and a voltage sense amplifier, and each second data sense amplifier associated with data lines of a second type, which lead from bit line sense amplifiers.

Abstract: Methods of terminating an external transmission line in a memory device having an on-die termination circuit include electrically coupling the termination circuit to the transmission line in response to a control signal which indicates that the memory device is in an active mode or a write mode. The termination circuit has an impedance value that is mismatched with an impedance value of the transmission line. The termination circuit can include an input/output pad, a resistor, and a transistor connected in series to a reference voltage. Also, the termination circuit may be electrically coupled to the transmission line by activating the transistor in the termination circuit to connect the transmission line to the reference voltage in response to the control signal. Related devices are also disclosed.

Abstract: The semiconductor memory device includes a plurality of first data sense amplifiers and a plurality of second data sense amplifiers. Each first data sense amplifier being a voltage sense amplifier, and each first data sense amplifier associated with data lines of a first type, which lead from bit line sense amplifiers. Each second data sense amplifier including a current sense amplifier and a voltage sense amplifier, and each second data sense amplifier associated with data lines of a second type, which lead from bit line sense amplifiers.

Abstract: A semiconductor memory device having reduced sensing noise and sensing current by reducing the number of cells activated by a word line is provided. The semiconductor memory device includes a memory cell array, which is segmented into a plurality of memory cell groups in a column direction, and a plurality of sub-word line drivers for selectively activating the sub-word line of a corresponding memory cell group in response to a group selection signal. The semiconductor memory device prevents sensing operation from occurring in a memory cell group which is not selected, while sensing operation is performed in a memory cell group which is selected by the group selection signal.

Abstract: An input buffer that can operate with Low Voltage Transistor-Transistor Logic (LVTTL) and with Stub Series Terminated transceiver Logic (SSTL) includes a differential amplifier that differentially amplifies a reference voltage and an external input signal. A switching system is coupled to the differential amplifier, to supply an external power supply voltage to the differential amplifier under SSTL operating conditions and to supply an internal power supply voltage to the differential amplifier under LVTTL operating conditions. An internal power supply voltage generator is responsive to the external power supply voltage, to generate the internal power supply voltage therefrom. The internal power supply voltage generator supplies the internal power supply voltage to the switching system. The switching system preferably includes a first switch that supplies the external power supply voltage to the differential amplifier in response to an SSTL control signal.