Patents by Inventor Sang-Ki Nam

Sang-Ki Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622195
    Abstract: A system and method of plasma processing includes a plasma processing system including a plasma chamber and a controller coupled to the plasma chamber. The plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric gas injection zones.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 14, 2020
    Assignee: Lam Research Corporation
    Inventors: Ryan Bise, Rajinder Dhindsa, Alexei Marakhtanov, Lumin Li, Sang Ki Nam, Jim Rogers, Eric Hudson, Gerardo Delgadino, Andrew D. Bailey, III, Mike Kellogg, Anthony Dela Llera, Darrell Ehrlich
  • Patent number: 10586686
    Abstract: Systems and methods are presented for a peripheral RF feed and symmetric RF return for symmetric RF delivery. According to one embodiment, a chuck assembly for plasma processing is provided. The chuck assembly includes an electrostatic chuck having a substrate support surface on a first side, and a facility plate coupled to the electrostatic chuck on a second side that is opposite the substrate support surface. A hollow RF feed is configured to deliver RF power, the hollow RF feed defined by a first portion contacting a periphery of the facility plate and a second portion coupled to the first portion, the second portion extending away from the chuck assembly.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: March 10, 2020
    Assignee: Law Research Corporation
    Inventors: Sang Ki Nam, Rajinder Dhindsa, James Rogers
  • Publication number: 20200072874
    Abstract: An RF sensing apparatus configured for use with a plasma processing chamber includes a penetration unit opened in an up/down direction, a main return path unit surrounding all or a portion of the penetration unit, and a secondary return path unit located between the penetration unit and the main return path unit, spaced apart from the main return path unit, and surrounding all or a portion of the penetration unit. The main return path unit and the secondary return path unit include a path through which a current flows in one of the up/down directions.
    Type: Application
    Filed: January 29, 2019
    Publication date: March 5, 2020
    Inventors: YOUNG DO KIM, SUNG YONG LIM, CHAN SOO KANG, DO HOON KWON, MIN JU KIM, SANG KI NAM, JUNG MO YANG, JONG HUN PI, KYU HEE HAN
  • Publication number: 20200035515
    Abstract: A cleaning solution production system is for cleaning a semiconductor substrate. The system includes a pressure tank, a plasma reaction tank configured to form a plasma in gas bubbles suspended in a decompressed liquid obtained from the pressure tank to thereby generate radical species in the decompressed liquid, a storage tank configured to store a cleaning solution containing the radical species generated in the plasma reaction tank, and a nozzle configured to supply the cleaning solution from the storage tank to a semiconductor substrate.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 30, 2020
    Inventors: Beom Jin YOO, Min Hyoung KIM, Sang Ki NAM, Won Hyuk JANG, Kyu Hee HAN, Young Do KIM, Jeong Min BANG
  • Publication number: 20200020551
    Abstract: A plasma generator, a cleaning liquid processing apparatus including the same, a semiconductor cleaning apparatus, and a cleaning liquid processing method are provided. The cleaning liquid processing apparatus comprising a bubble formation section configured to lower a pressure of a mixed liquid obtained by mixing a liquid and a gas to form bubbles in the mixed liquid, a plasma generator connected to the bubble formation section and configured to apply a voltage to the mixed liquid to form plasma in the bubbles formed in the mixed liquid, a mixing section connected to the plasma generator and configured to dissolve radicals included in the plasma into the mixed liquid, and a discharge nozzle connected to the mixing section and configured to discharge the mixed liquid to a wafer.
    Type: Application
    Filed: May 24, 2019
    Publication date: January 16, 2020
    Inventors: Beom Jin YOO, Min Hyoung KIM, Sang Ki NAM, Lu SIQING, Won Hyuk JANG, Kyu Hee HAN
  • Patent number: 10522332
    Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeongkwang Lee, Sunggil Kang, Sang Ki Nam, Kwangyoub Heo, Kyuhee Han
  • Publication number: 20190287792
    Abstract: A method of manufacturing an integrated circuit (IC) device includes exposing a partial region of a photoresist film formed on a main surface of a substrate to generate acid, and diffusing the acid in the partial region of the photoresist film. Diffusing the acid may include applying an electric field, in a direction perpendicular to a direction in which the main surface of the substrate extends, to the photoresist film using an electrode facing the substrate through an electric-field transmission layer filling between the photoresist film and the electrode. The electric-field transmission layer may include an ion-containing layer or a conductive polymer layer.
    Type: Application
    Filed: October 19, 2018
    Publication date: September 19, 2019
    Applicant: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Jin PARK, Sang Ki NAM, Kyu-hee HAN, Jin-ok KIM, Jin-hong PARK, Gwang-we YOO
  • Publication number: 20190279846
    Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Yeongkwang LEE, Sunggil KANG, Sang Ki NAM, Kwangyoub HEO, Kyuhee HAN
  • Patent number: 10410874
    Abstract: In a plasma processing method, a substrate is loaded onto a substrate electrode within a chamber, the substrate having an object layer to be etched thereon. A plasma generating power output is applied to form plasma within the chamber. A first bias power output is applied to the substrate electrode to perform a first etch stage on the object layer. A second bias power output having a nonsinusoidal voltage waveform is applied to the substrate electrode to perform a second etch stage on the object layer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Beom Jin Yoo, Sang Ki Nam, Kwang-Youb Heo, Jehun Woo, Sang-Heon Lee, Masahiko Tomita, Vasily Pashkovskiy
  • Patent number: 10347468
    Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeongkwang Lee, Sunggil Kang, Sang Ki Nam, Kwangyoub Heo, Kyuhee Han
  • Publication number: 20190181020
    Abstract: There are provided a method of forming a nanorod structures and a method of forming a semiconductor device. The method of forming a semiconductor device may include forming a first seed pattern on a substrate; forming a first nanorod structure on the first seed pattern; and forming a molded structure surrounding a first lateral surface of the first nanorod structure while exposing a first upper surface of the first nanorod structure. The first nanorod structure may include a plurality of nanorods stacked sequentially on the first seed pattern. The plurality of nanorods may include a lowermost nanorod grown from the first seed pattern, and upper nanorods formed on the lowermost nanorod. The molded structure may include a lowermost molded layer surrounding a second lateral surface of the lowermost nanorod, and upper molded layers stacked sequentially on the lowermost molded layer. The upper molded layers may be formed of different materials.
    Type: Application
    Filed: June 26, 2018
    Publication date: June 13, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byeong Hwan JEON, Sang Ki NAM
  • Publication number: 20190122867
    Abstract: A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.
    Type: Application
    Filed: May 29, 2018
    Publication date: April 25, 2019
    Inventors: Sang Ki Nam, Sunggil Kang, Sungyong Lim, Beomjin Yoo, Akira Koshiishi, Vasily Pashkovskiy, Kwangyoub Heo
  • Publication number: 20190122860
    Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
    Type: Application
    Filed: January 12, 2018
    Publication date: April 25, 2019
    Inventors: YEONGKWANG LEE, Sunggil KANG, Sang Ki NAM, Kwangyoub HEO, KYUHEE HAN
  • Publication number: 20190122866
    Abstract: Disclosed are a plasma processing apparatus and a method of manufacturing a semiconductor device using the same. The plasma processing apparatus comprises a chamber, an electrostatic chuck in the chamber and loading a substrate, a plasma electrode generating an upper plasma on the electrostatic chuck; and a hollow cathode between the plasma electrode and the electrostatic chuck, wherein the hollow cathode generates a lower plasma below the upper plasma. The hollow cathode comprises cathode holes each having a size less than a thickness of a plasma sheath of the upper plasma.
    Type: Application
    Filed: May 18, 2018
    Publication date: April 25, 2019
    Inventors: Sang Ki Nam, Akira KOSHIISHI, Kwangyoub HEO, Sunggil KANG, Beomjin YOO, Sungyong LIM, Vasily PASHKOVSKIY
  • Publication number: 20190096636
    Abstract: A plasma processing apparatus includes a chamber including a space for processing a substrate, a substrate stage supporting the substrate within the chamber and including a lower electrode, an upper electrode within the chamber facing the lower electrode, a first power supply including a sinusoidal wave power source configured to apply a sinusoidal wave power to the lower electrode to form plasma within the chamber, and a second power supply configured to apply a nonsinusoidal wave power to the upper electrode to generate an electron beam.
    Type: Application
    Filed: March 29, 2018
    Publication date: March 28, 2019
    Inventors: Sang Ki NAM, Sung Yong LIM, Beomjin YOO, Jongwoo SUN, Kyuhee HAN, Kwangyoub HEO, Je-Woo HAN
  • Publication number: 20190035606
    Abstract: In a plasma processing method, a substrate is loaded onto a substrate electrode within a chamber, the substrate having an object layer to be etched thereon. A plasma generating power output is applied to form plasma within the chamber. A first bias power output is applied to the substrate electrode to perform a first etch stage on the object layer. A second bias power output having a nonsinusoidal voltage waveform is applied to the substrate electrode to perform a second etch stage on the object layer.
    Type: Application
    Filed: January 10, 2018
    Publication date: January 31, 2019
    Inventors: Beom Jin Yoo, Sang Ki Nam, Kwang-Youb Heo, Jehun Woo, Sang-Heon Lee, Masahiko Tomita, Vasily Pashkovskiy
  • Patent number: 10048589
    Abstract: Embodiments described herein generally relate to methods for mitigating patterning defects. More specifically, embodiments described herein relate to utilizing field guided post exposure bake processes to mitigate microbridge photoresist defects. An electric field may be applied to a substrate being processed during a post exposure bake process. Photoacid generated as a result of the exposure may be moved along a direction defined by the electric field. The movement of the photoacid may contact microbridge defects and facilitate the removal of the microbridge defects from the surface of a substrate.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 14, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Ludovic Godet, Sang Ki Nam, Christine Y. Ouyang
  • Patent number: 9996006
    Abstract: Methods disclosed herein provide apparatus and methods for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes. In one embodiment, an apparatus includes a processing chamber configured to apply an electric field to a substrate via a non-gas phase intermediate medium. Methods described herein include dissociation of a photoacid generator to generate anions and cations. The anions may be moved within the photoresist layer by the electric field to more precisely control the speed and location of acid generation and regeneration processes.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: June 12, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christine Y. Ouyang, Sang Ki Nam, Ludovic Godet
  • Publication number: 20180107117
    Abstract: Methods disclosed herein provide apparatus and methods for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes. In one embodiment, an apparatus includes a processing chamber configured to apply an electric field to a substrate via a non-gas phase intermediate medium. Methods described herein include dissociation of a photoacid generator to generate anions and cations. The anions may be moved within the photoresist layer by the electric field to more precisely control the speed and location of acid generation and regeneration processes.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 19, 2018
    Inventors: Christine Y. OUYANG, Sang Ki NAM, Ludovic GODET
  • Patent number: 9927709
    Abstract: Methods disclosed herein provide apparatus and methods for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes. In one embodiment, an apparatus includes a processing chamber configured to apply an electric field to a substrate via a non-gas phase intermediate medium. Methods described herein include dissociation of a photoacid generator to generate anions and cations. The anions may be moved within the photoresist layer by the electric field to more precisely control the speed and location of acid generation and regeneration processes.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: March 27, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Christine Y. Ouyang, Sang Ki Nam, Ludovic Godet