Abstract: A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least one command line and a plurality of data lines, and includes a non-volatile memory, a command packet decoder, and a control unit, such that the non-volatile memory stores data, the command packet decoder receives command packets through a command line and outputs command information by decoding the received command packets, the command packet decoder receives a data transmit command packet or a data request command packet and outputs a write command or a read command, address information, and data bus width information, the control unit performs a control operation in response to the command information and selects all or some of the plurality of data lines in response to the data bus width information and receives or transmits the data through the selected data line, and controls data writing or reading of the non-

Abstract: The present invention relates to methods of production of the completely post-translationally modified protein by combination of cell-free protein synthesis and cell-free co- and post-translational modification. Previous cell-free protein synthesis system has only been capable of producing partially post-translationally modified protein but the present invention employs a co- and post-translational modification machinery that produces completely post-translationally modified protein.

Abstract: The present invention relates to methods of production of the completely post-translationally modified protein by combination of cell-free protein synthesis and cell-free co- and post-translational modification. Previous cell-free protein synthesis system has only been capable of producing partially post-translationally modified protein but the present invention employs a co- and post-translational modification machinery that produces completely post-translationally modified protein.

Abstract: A method and apparatus for numerically analyzing a growth degree of grains grown on a surface of a semiconductor wafer, in which the growth degree of grains is automatically calculated and numerated through a computer by using an image file of the surface of the semiconductor wafer scanned by an SEM. A predetermined portion of a surface of the wafer is scanned using the SEM, and the scanned SEM image is simultaneously stored into a database. An automatic numerical program applies meshes to an analysis screen frame and selects an analysis area on a measured image. Thereafter, a smoothing process for reducing an influence of noise is performed on respective pixels designated by the meshes using an average value of image data of adjacent pixels. A standardization process is then performed, based on respective images in order to remove a brightness difference between the measured images.

Abstract: A film thickness standard (FTS) comprises an oxide film formed on a semiconductor substrate with a thickness over 1 &mgr;m. A method of preparing an oxide film thickness standard reference of semiconductor device is carried out by repeatedly and continuously performing the formation process of the oxide film under the same processing conditions thereby to form the oxide film on a semiconductor substrate with a thickness over a certain level.

Abstract: Scanning Electron Microscope (SEM) analysis is used to detect undesired conductive material on the gate sidewall spacers. The undesired conductive material is then etched from the sidewall spacers if the undesired material is detected by the SEM analysis. More specifically, integrated circuit field effect transistors may be manufactured by forming on an integrated circuit substrate, a plurality of field effect transistors, each comprising spaced apart source and drain regions, a gate therebetween including a sidewall, a sidewall spacer on the sidewall and contacts comprising conductive material on the source and drain regions. At least one of the field effect transistors may include undesired conductive material on the sidewall spacer thereof. The integrated circuit field effect transistors are tested by performing SEM analysis on the integrated circuit substrate to detect the undesired conductive material on the sidewall spacer.

Abstract: A submicron level dimension reference for use with a scanning electron microscope in a semiconductor device fabrication apparatus. The reference has a first insulating layer with a first pattern formed on a semiconductor wafer substrate. A plurality of contacts are formed between the first pattern of the first insulating layer such that the contacts directly communicate the wafer substrate. The contacts are capable of carrying an electrical charge. An electrically conductive layer is formed over the contacts and the first insulating layer. A second insulating layer with a second pattern is formed over the conductive layer. Electrical charges generated by radiating the scanning electron microscope on the submicron level dimension reference are transferred from the first and second insulating layers to the wafer substrate via the conductive layer and the plurality of contacts.

Abstract: A film thickness standard (FTS) comprises an oxide film formed on a semiconductor substrate with a thickness over 1 .mu.m. A method of preparing an oxide film thickness standard reference of semiconductor device is carried out by repeatedly and continuously performing the formation process of the oxide film under the same processing conditions thereby to form the oxide film on a semiconductor substrate with a thickness over a certain level.

Abstract: A method for testing a contact opening of a semiconductor device includes the steps of: inspecting a wafer using an in-line scanning electron microscope, comparing a contrast difference of contact opening regions displayed on the scanning electron microscope, and determining whether the processes for forming the contact openings have been performed correctly based on results of the comparison step. The test method may be performed after any of a contact photolithography process, contact etching process, or conductive layer etching process.

Abstract: A fuse signature circuit for a microelectronic device includes a fuse circuit and a sensing circuit. The fuse circuit includes a fuse which can be cut electrically in response to a cut control signal, and the fuse circuit generates a fuse state signal indicating if the fuse has been cut. The sensing circuit generates an output signal responsive to the fuse state signal.

Abstract: A self refresh circuit for an integrated circuit memory device includes a programmable refresh circuit, a plurality of counters, and a refresh cycle selection circuit. The programmable refresh circuit can be electrically programmed to generate one of a plurality of refresh control signals. A first one of the counters generates a first oscillating output signal having a first predetermined period and each successive counter generates a respective oscillating output signal having a respective period twice that of a respective preceding counter. The refresh cycle selection circuit selects a self refresh cycle from one of the oscillating output signals in response to the refresh control signal generated by the at least one programmable refresh circuit. Related methods are also disclosed.

Abstract: A test control circuit and method of testing a memory cell in a semiconductor memory device. The test control circuit includes a memory cell array having a plurality of normal memory cells to store data on a semiconductor substrate and a plurality of redundancy memory cells to substitute for defective normal memory cells. Row and column redundancy fuse boxes include fuse elements to be electrically fused to enable row and column redundancy decoders for selecting rows and columns of the redundancy memory cells. A redundancy cell test signal generator generates, in response to a test signal applied to an extra line in the address bus, a master clock for testing the redundancy memory cell under the same mode as a test mode of the normal memory cell. A test controller provides an enable signal for selecting the redundancy memory cells of a memory array in response to logic levels of the master clock and an address signal applied during the redundancy memory cell test.