Patents by Inventor Sang-Oh Lee
Sang-Oh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120187994Abstract: System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.Type: ApplicationFiled: January 21, 2011Publication date: July 26, 2012Applicant: QUALCOMM INCORPORATEDInventors: Jeongsik Yang, Chan Hong Park, Sang-oh Lee
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Patent number: 8187952Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so that the hard mask layer becomes a protrusion, forming spacers covering both sides of the protrusion, removing one of the spacers using a doped etch barrier as an etch barrier, and etching the gap-fill layer using a remaining spacer as an etch barrier to form a side trench exposing one side of the active region.Type: GrantFiled: December 24, 2009Date of Patent: May 29, 2012Assignee: Hynix Semiconductor Inc.Inventors: Uk Kim, Sang-Oh Lee
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Patent number: 8170506Abstract: Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions.Type: GrantFiled: July 29, 2008Date of Patent: May 1, 2012Assignee: Qualcomm IncorporatedInventors: Bahman Ahrari, Hee Choul Lee, Jin-Su Ko, Sang Oh Lee
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Patent number: 8143958Abstract: Methods and apparatus for self testing a multiband voltage controlled oscillator (VCO) are disclosed. A tuning voltage of the VCO is adjusted where the output of the VCO does not affect the input to the VCO. Frequency bands in the VCO are selected. Output frequencies of the VCO are measured.Type: GrantFiled: May 20, 2009Date of Patent: March 27, 2012Assignee: QUALCOMM, IncorporatedInventors: Jeongsik Yang, Jin Wook Kim, Hong Sun Kim, Sang-Oh Lee
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Publication number: 20110291716Abstract: In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.Type: ApplicationFiled: August 12, 2011Publication date: December 1, 2011Applicant: QUALCOMM IncorporatedInventors: Shen Wang, Sang-Oh Lee, Jeongsik Yang
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Publication number: 20110294275Abstract: A method for fabricating a semiconductor device includes forming an isolation layer over a substrate, forming a plurality of open regions exposing the substrate by selectively etching the isolation layer, performing a surface treatment over the isolation layer, expanding the open regions by removing the surface-treated portion of the isolation layer, and forming a conductive layer in the expanded open regions.Type: ApplicationFiled: July 8, 2010Publication date: December 1, 2011Inventor: Sang-Oh Lee
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Patent number: 8022780Abstract: Techniques for compensating for the effects of temperature change on voltage controlled oscillator (VCO) frequency are disclosed. In an embodiment, an auxiliary varactor is coupled to an LC tank of the VCO. The auxiliary varactor has a capacitance controlled by a temperature-dependant control voltage to minimize the overall change in VCO frequency with temperature. Techniques for generating the control voltage using digital and analog means are further disclosed.Type: GrantFiled: April 22, 2008Date of Patent: September 20, 2011Assignee: QUALCOMM IncorporatedInventors: Mazhareddin Taghivand, Conor Donovan, Jeongsik Yang, Sang-Oh Lee
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Patent number: 8018269Abstract: In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.Type: GrantFiled: December 10, 2007Date of Patent: September 13, 2011Assignee: QUALCOMM IncorporatedInventors: Shen Wang, Sang-Oh Lee, Jeongsik Yang
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Patent number: 8012881Abstract: A method for forming contact holes in a semiconductor device includes forming a hard mask layer over an etch target layer, forming a first line pattern in the hard mask layer by etching a portion of the hard mask layer through a primary etch process, forming a second line pattern crossing the first line pattern by etching the hard mask layer including the first line pattern through a secondary etch process, and etching the etch target layer by using the hard mask layer including the first line pattern and the second line pattern as an etch barrier.Type: GrantFiled: August 11, 2010Date of Patent: September 6, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sang-Oh Lee, Sung-Kwon Lee, Jun-Hyeub Sun, Jong-Sik Bang
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Publication number: 20110130004Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer.Type: ApplicationFiled: May 11, 2010Publication date: June 2, 2011Inventor: Sang-Oh LEE
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Publication number: 20110129975Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench.Type: ApplicationFiled: December 30, 2009Publication date: June 2, 2011Inventor: Sang-Oh LEE
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Publication number: 20110104894Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so that the hard mask layer becomes a protrusion, forming spacers covering both sides of the protrusion, removing one of the spacers using a doped etch barrier as an etch barrier, and etching the gap-fill layer using a remaining spacer as an etch barrier to form a side trench exposing one side of the active region.Type: ApplicationFiled: December 24, 2009Publication date: May 5, 2011Inventors: Uk KIM, Sang-Oh Lee
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Patent number: 7936220Abstract: Techniques for improving the linearity of a cascode amplifier. In an exemplary embodiment, an auxiliary common-gate amplifier is provided in parallel with the principal cascode branch. The auxiliary common-gate amplifier samples a cascoded node in the principal cascode branch. The auxiliary common-gate amplifier generates a current which, when combined with the current generated by the principal cascode branch, cancels a distortion component to generate an output current with improved linearity characteristics. In an exemplary embodiment, a phase shifting network couples the cascoded node to the auxiliary common-gate amplifier, and may include, e.g., a capacitor coupled to an inductor.Type: GrantFiled: December 12, 2008Date of Patent: May 3, 2011Assignee: QUALCOMM, IncorporatedInventors: Xiaoyong Li, Sang-Oh Lee, Cormac S. Conroy
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Patent number: 7855610Abstract: Techniques are disclosed for trimming a capacitance associated with a capacitor bank for use in a voltage-controlled oscillator (VCO). In an embodiment, each capacitance is sub-divided into a plurality of constituent capacitances. The constituent capacitances may be selectively enabled or disabled to trim the step sizes of the capacitor bank. Further techniques are disclosed for calibrating the trimmable capacitance to minimize step size error for the capacitor bank.Type: GrantFiled: May 7, 2008Date of Patent: December 21, 2010Assignee: QUALCOMM IncorporatedInventors: Mazhareddin Taghivand, Jeongsik Yang, Sang-Oh Lee
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Patent number: 7851947Abstract: A circuit which selects a supply voltage from a plurality of voltage supplies is presented. The circuit includes a first transistor configured to select a first voltage supply, a second transistor configured to select a second voltage supply, a first parasitic current inhibitor coupled the first transistor, the first voltage supply, and the second voltage supply, where the first parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the first transistor, and a second parasitic current inhibitor coupled the second transistor, the first voltage supply, and the second voltage supply, where the second parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the second transistor.Type: GrantFiled: November 5, 2007Date of Patent: December 14, 2010Assignee: QUALCOMM, IncorporatedInventors: Marco Cassia, Aristotele Hadjichristos, Conor Donovan, Sang-Oh Lee
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Publication number: 20100295622Abstract: Methods and apparatus for self testing a multiband voltage controlled oscillator (VCO) are disclosed. A tuning voltage of the VCO is adjusted where the output of the VCO does not affect the input to the VCO. Frequency bands in the VCO are selected. Output frequencies of the VCO are measured.Type: ApplicationFiled: May 20, 2009Publication date: November 25, 2010Applicant: QUALCOMM IncorporatedInventors: Jeongsik Yang, Jin Wook Kim, Hong Sun Kim, Sang-Oh Lee
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Publication number: 20100225402Abstract: Techniques for setting a fine tuning input signal Vtune for a voltage-controlled oscillator (VCO) in a coarse tuning mode of the VCO. In an exemplary embodiment, the fine tuning input signal during coarse tuning mode is made temperature-dependent to account for possible variation of Vtune over temperature during fine tuning mode. Methods and apparatuses employing the techniques are further described.Type: ApplicationFiled: March 9, 2009Publication date: September 9, 2010Applicant: QUALCOMM IncorporatedInventors: Jeongsik Yang, Jin Wook Kim, Sang-Oh Lee
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Publication number: 20100148873Abstract: Techniques for improving the linearity of a cascode amplifier. In an exemplary embodiment, an auxiliary common-gate amplifier is provided in parallel with the principal cascode branch. The auxiliary common-gate amplifier samples a cascoded node in the principal cascode branch. The auxiliary common-gate amplifier generates a current which, when combined with the current generated by the principal cascode branch, cancels a distortion component to generate an output current with improved linearity characteristics. In an exemplary embodiment, a phase shifting network couples the cascoded node to the auxiliary common-gate amplifier, and may include, e.g., a capacitor coupled to an inductor.Type: ApplicationFiled: December 12, 2008Publication date: June 17, 2010Applicant: QUALCOMM IncorporatedInventors: Xiaoyong Li, Sang-Oh Lee, Cormac S. Conroy
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Publication number: 20100055922Abstract: A method for fabricating a semiconductor device improves the variation in critical dimensions of neighboring patterns when employing a negative SPT process. The method includes forming an etch stop layer on an etch target layer, forming a first hard mask pattern on the etch stop layer, forming a spacer pattern on a sidewall of the first hard mask pattern, forming a second hard mask layer on an entire surface of a resultant structure including the spacer pattern, forming a second hard mask pattern by etching the second hard mask layer up to a height of the first hard mask pattern, removing the spacer pattern, and forming a pattern by etching the etch stop layer and the etch target layer using the first and the second hard mask patterns as an etch barrier.Type: ApplicationFiled: June 25, 2009Publication date: March 4, 2010Inventors: Tae-Hyoung Kim, Jun-Hyeub Sun, Sang-Oh Lee
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Publication number: 20100026383Abstract: Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Applicant: QUALCOMM IncorporatedInventors: Bahman Ahrari, Hee Choul Lee, Jin-Su Ko, Sang Oh Lee