Patents by Inventor Sang Oh Lim

Sang Oh Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10936040
    Abstract: A semiconductor apparatus includes a clock control circuit that at least one of generates a plurality of latch control clocks, which are periodically transitioned, in response to a power saving mode signal and a clock, and individually locks each of the plurality of latch control clocks to one of multiple levels regardless of the clock. The semiconductor apparatus also includes a latch circuit that stores an input signal in response to the plurality of latch control clocks and outputs the stored signal as an output signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 10916277
    Abstract: A memory device includes a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information; a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device; a peripheral circuit performing a read operation on the storage block; and a control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Oh Lim
  • Publication number: 20200143856
    Abstract: A memory device includes a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information; a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device; a peripheral circuit performing a read operation on the storage block; and a control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information.
    Type: Application
    Filed: August 23, 2019
    Publication date: May 7, 2020
    Inventor: Sang Oh LIM
  • Publication number: 20190369692
    Abstract: A semiconductor apparatus includes a clock control circuit that at least one of generates a plurality of latch control clocks, which are periodically transitioned, in response to a power saving mode signal and a clock, and individually locks each of the plurality of latch control clocks to one of multiple levels regardless of the clock. The semiconductor apparatus also includes a latch circuit that stores an input signal in response to the plurality of latch control clocks and outputs the stored signal as an output signal.
    Type: Application
    Filed: December 20, 2018
    Publication date: December 5, 2019
    Applicant: SK hynix Inc.
    Inventor: Sang Oh LIM
  • Patent number: 10168370
    Abstract: A semiconductor apparatus includes an input/output pad configured to exchange signals with an external device; a control pad configured to be inputted with a discharge signal from the external device; and a first electrostatic protection unit configured to form an electrostatic discharge path from the input/output pad to a first voltage supply line according to the discharge signal.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 1, 2019
    Assignee: SK hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 10074412
    Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a delay code determining unit configured to output a final delay trim code reflecting process, voltage and temperature (PVT) conditions of the semiconductor memory device, using an internal clock generated for a reference time and a delay circuit configured to reflect a delay of a data line on a clock signal in response to the final delay trim code.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 10002667
    Abstract: A memory device may include N memory areas that are divided into a first group and a second group, and are selected by area selection signals corresponding to the N memory areas among N area selection signals, N*M pipe latches that store output data of memory areas corresponding to the N*M pipe latches among the N memory areas, a first pipe output signal generation circuit that generates 1-1th to 1-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the first group, in response to an area selection signal corresponding to a predetermined memory area of memory areas, and a second pipe output signal generation circuit that generates 2-1th to 2-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the second group, in response to an area selection signal corresponding to a predetermined memory area of memory areas.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 19, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sang-Oh Lim, Jong-Tai Park
  • Publication number: 20180144781
    Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a delay code determining unit configured to output a final delay trim code reflecting process, voltage and temperature (PVT) conditions of the semiconductor memory device, using an internal clock generated for a reference time and a delay circuit configured to reflect a delay of a data line on a clock signal in response to the final delay trim code.
    Type: Application
    Filed: June 21, 2017
    Publication date: May 24, 2018
    Inventor: Sang Oh LIM
  • Publication number: 20180136860
    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, and a peripheral circuit disposed under the memory cell array. The peripheral circuit may include a bit line contact region electrically coupled to the memory cell array, a first page buffer group disposed on a first side portion of the bit line contact region, and a second page buffer group disposed on a second side portion of the bit line contact region.
    Type: Application
    Filed: March 28, 2017
    Publication date: May 17, 2018
    Applicant: SK hynix Inc.
    Inventor: Sang Oh LIM
  • Patent number: 9514790
    Abstract: A data transmission circuit may include data line groups and pass sections arranged among the data line groups to allow the data line groups to form one line. The data transmission circuit may include an input/output unit configured to be coupled to the data line groups and to process write data to be transmitted to the data line groups or read data transmitted from the data line groups. The data transmission circuit may include a pass control unit configured to selectively enable the pass sections in response to an address for specifying a target data line group of the data line groups.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 6, 2016
    Assignee: SK HYNIX INC.
    Inventor: Sang Oh Lim
  • Patent number: 9514793
    Abstract: A semiconductor memory device includes a plurality of data buffering units corresponding to a data line, wherein the data buffering units include a first data buffering unit suitable for latching data stored in a memory cell in a data read operation, and second data buffering units, an output unit suitable for outputting the data latched in the first data buffering unit, and a control block suitable for controlling a current path to be formed between the second data buffering units and the output unit in the data read operation.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sang-Oh Lim
  • Patent number: 9508445
    Abstract: An operating method of a semiconductor device includes applying a read voltage to a selected word line of a selected memory block, among a plurality of memory blocks including cell strings coupled between bit lines and a source line, detecting a voltage of the source line by forming a channel in cell strings of the selected memory block, comparing the voltage of the source line with a reference voltage corresponding to the selected memory block, and performing a least significant bit (LSB) read operation on memory cells coupled to the selected word line when the voltage of the source line is greater than the reference voltage, as a result of the comparing, and performing a most significant bit (MSB) read operation on the memory cells when the voltage of the source line is less than the reference voltage, as the result of the comparing.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: November 29, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 9496055
    Abstract: A semiconductor memory device includes a plurality of memory cells arranged in a row direction and a column direction, a plurality of word lines each connected to memory cells in a row among the memory cells, and a majority of bit lines each connected to memory cells in a column among the memory cells. One or more memory cells are distributed as flag cells among memory cells connected to each word line, and flag cells connected to a first word line and flag cells connected to a second word line that is disposed adjacent to the first word line among the word lines are connected to first and second bit lines, respectively.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: November 15, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 9484108
    Abstract: An integrated circuit includes an internal circuit including a input/output unit suitable for inputting/outputting data, and a voltage supplying circuit suitable for supplying a first operating voltage to the internal circuit in response to a first control signal during a general operation, and supplying a second operating voltage that is higher than the first operating voltage to the input/output unit in response to a second control signal during an output of the data.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: November 1, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 9472297
    Abstract: A semiconductor memory device includes a memory cell part including a main memory unit and a redundancy memory unit, a page buffer circuit including a plurality of page buffer groups and reading data stored in the memory cell part, and a sensing circuit including a plurality of sense amplifiers corresponding to the plurality of page buffer groups, respectively, and suitable for sensing the read data, wherein the plurality of sense amplifiers perform data sensing operations in parallel in order to sense the read data.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: October 18, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 9443618
    Abstract: Provided is a semiconductor memory device that may efficiently map an internal address used inside the semiconductor memory device in response to an external address that is applied from the outside of the semiconductor memory device. The semiconductor memory device may include a memory cell array configured to include a first main cell array, a first spare cell array, a second main cell array, and a second spare cell array each of which has internal cells that are selected in response to an internal address, and an address mapping unit configured to map external address as the internal address when the external address designates the first main and spare cell arrays, and to operate calculation with a given value and the external address and to map the calculation result value as the internal address when the external address designates the second main and spare cell arrays.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 13, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sang-Oh Lim
  • Publication number: 20160225417
    Abstract: A data transmission circuit may include data line groups and pass sections arranged among the data line groups to allow the data line groups to form one line. The data transmission circuit may include an input/output unit configured to be coupled to the data line groups and to process write data to be transmitted to the data line groups or read data transmitted from the data line groups. The data transmission circuit may include a pass control unit configured to selectively enable the pass sections in response to an address for specifying a target data line group of the data line groups.
    Type: Application
    Filed: May 13, 2015
    Publication date: August 4, 2016
    Inventor: Sang Oh LIM
  • Publication number: 20160180947
    Abstract: A semiconductor memory device includes a memory cell part including a main memory unit and a redundancy memory unit, a page buffer circuit including a plurality of page buffer groups and reading data stored in the memory cell part, and a sensing circuit including a plurality of sense amplifiers corresponding to the plurality of page buffer groups, respectively, and suitable for sensing the read data, wherein the plurality of sense amplifiers perform data sensing operations in parallel in order to sense the read data.
    Type: Application
    Filed: May 28, 2015
    Publication date: June 23, 2016
    Inventor: Sang Oh LIM
  • Publication number: 20160172012
    Abstract: A semiconductor memory device includes a plurality of data buffering units corresponding to a data line, wherein the data buffering units include a first data buffering unit suitable for latching data stored in a memory cell in a data read operation, and second data buffering units, an output unit suitable for outputting the data latched in the first data buffering unit, and a control block suitable for controlling a current path to be formed between the second data buffering units and the output unit in the data read operation.
    Type: Application
    Filed: June 4, 2015
    Publication date: June 16, 2016
    Inventor: Sang-Oh LIM
  • Publication number: 20160125949
    Abstract: An operating method of a semiconductor device includes applying a read voltage to a selected word line of a selected memory block, among a plurality of memory blocks including cell strings coupled between bit lines and a source line, detecting a voltage of the source line by forming a channel in cell strings of the selected memory block, comparing the voltage of the source line with a reference voltage corresponding to the selected memory block, and performing a least significant bit (LSB) read operation on memory cells coupled to the selected word line when the voltage of the source line is greater than the reference voltage, as a result of the comparing, and performing a most significant bit (MSB) read operation on the memory cells when the voltage of the source line is less than the reference voltage, as the result of the comparing.
    Type: Application
    Filed: April 3, 2015
    Publication date: May 5, 2016
    Inventor: Sang Oh LIM