Abstract: A system for manufacturing edible food products according to the present disclosure includes a first food ingredient supply apparatus configured to separate a single sheet of a first food ingredient from a first food ingredient stack including a plurality of stacked first food ingredients and supply the single sheet of first food ingredient, a second food ingredient supply apparatus configured to separate a single sheet of a second food ingredient from a second food ingredient stack including a plurality of stacked second food ingredients and supply the single sheet of second food ingredient, and a pressing device configured to form an edible food product by pressing a semi-finished product formed by seating the supplied single sheet of the first food ingredient on the supplied single sheet of the second food ingredient.

Abstract: An apparatus for supplying food ingredients according to the present disclosure includes a food ingredient lifting part configured to separate and move upward a food ingredient stack from a food ingredient cassette on which food ingredients including a plurality of stacked food ingredients are seated, a food ingredient separation part configured to suck and move upward a single sheet of a food ingredient from the food ingredient stack moved upward by the food ingredient lifting part, and a horizontal movement part configured to transfer forward the single sheet of the food ingredient moved upward by the food ingredient separation part.

Abstract: A cutting apparatus according to the present disclosure includes a cutting roller including a cutting body having a cylindrical shape and configured to rotate about an axis defined in a leftward/rightward direction, and cutting blades protruding outward in a radial direction of the cutting body further than a surface of the cutting body to cut an edible food product provided in a forward/rearward direction, and a cutting base part disposed at a position facing the cutting roller based on the edible food product to support the edible food product to be cut by the cutting roller.

Abstract: A display device comprises a substrate; a driving transistor including a first active layer and a switching transistor including a second active layer, the first active layer and the second active layer being disposed on the substrate; a first gate insulating layer disposed on the first active layer of the driving transistor and the second active layer of the switching transistor; first and second gate electrodes disposed on the first gate insulating layer to overlap the first active layer of the driving transistor and the second active layer of the switching transistor, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; and a second interlayer insulating layer disposed on the first interlayer insulating layer to overlap the first active layer without overlapping the second active layer in a plan view.

Abstract: A shoe management apparatus capable of managing various types of shoes and including a cabinet defining an inner space for storing shoes; and a partition dividing the inner space into an upper first compartment and a lower second compartment, formed therein with a fluid path along which air is discharged into the inner space, and variable in length with respect to a front-to-rear direction of the shoe management apparatus.

Abstract: A semiconductor apparatus includes a clock control circuit that at least one of generates a plurality of latch control clocks, which are periodically transitioned, in response to a power saving mode signal and a clock, and individually locks each of the plurality of latch control clocks to one of multiple levels regardless of the clock. The semiconductor apparatus also includes a latch circuit that stores an input signal in response to the plurality of latch control clocks and outputs the stored signal as an output signal.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information; a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device; a peripheral circuit performing a read operation on the storage block; and a control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information; a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device; a peripheral circuit performing a read operation on the storage block; and a control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information.

Abstract: A semiconductor apparatus includes a clock control circuit that at least one of generates a plurality of latch control clocks, which are periodically transitioned, in response to a power saving mode signal and a clock, and individually locks each of the plurality of latch control clocks to one of multiple levels regardless of the clock. The semiconductor apparatus also includes a latch circuit that stores an input signal in response to the plurality of latch control clocks and outputs the stored signal as an output signal.

Abstract: A semiconductor apparatus includes an input/output pad configured to exchange signals with an external device; a control pad configured to be inputted with a discharge signal from the external device; and a first electrostatic protection unit configured to form an electrostatic discharge path from the input/output pad to a first voltage supply line according to the discharge signal.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a delay code determining unit configured to output a final delay trim code reflecting process, voltage and temperature (PVT) conditions of the semiconductor memory device, using an internal clock generated for a reference time and a delay circuit configured to reflect a delay of a data line on a clock signal in response to the final delay trim code.

Abstract: A memory device may include N memory areas that are divided into a first group and a second group, and are selected by area selection signals corresponding to the N memory areas among N area selection signals, N*M pipe latches that store output data of memory areas corresponding to the N*M pipe latches among the N memory areas, a first pipe output signal generation circuit that generates 1-1th to 1-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the first group, in response to an area selection signal corresponding to a predetermined memory area of memory areas, and a second pipe output signal generation circuit that generates 2-1th to 2-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the second group, in response to an area selection signal corresponding to a predetermined memory area of memory areas.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a delay code determining unit configured to output a final delay trim code reflecting process, voltage and temperature (PVT) conditions of the semiconductor memory device, using an internal clock generated for a reference time and a delay circuit configured to reflect a delay of a data line on a clock signal in response to the final delay trim code.

Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, and a peripheral circuit disposed under the memory cell array. The peripheral circuit may include a bit line contact region electrically coupled to the memory cell array, a first page buffer group disposed on a first side portion of the bit line contact region, and a second page buffer group disposed on a second side portion of the bit line contact region.

Abstract: A data transmission circuit may include data line groups and pass sections arranged among the data line groups to allow the data line groups to form one line. The data transmission circuit may include an input/output unit configured to be coupled to the data line groups and to process write data to be transmitted to the data line groups or read data transmitted from the data line groups. The data transmission circuit may include a pass control unit configured to selectively enable the pass sections in response to an address for specifying a target data line group of the data line groups.

Abstract: A semiconductor memory device includes a plurality of data buffering units corresponding to a data line, wherein the data buffering units include a first data buffering unit suitable for latching data stored in a memory cell in a data read operation, and second data buffering units, an output unit suitable for outputting the data latched in the first data buffering unit, and a control block suitable for controlling a current path to be formed between the second data buffering units and the output unit in the data read operation.

Abstract: An operating method of a semiconductor device includes applying a read voltage to a selected word line of a selected memory block, among a plurality of memory blocks including cell strings coupled between bit lines and a source line, detecting a voltage of the source line by forming a channel in cell strings of the selected memory block, comparing the voltage of the source line with a reference voltage corresponding to the selected memory block, and performing a least significant bit (LSB) read operation on memory cells coupled to the selected word line when the voltage of the source line is greater than the reference voltage, as a result of the comparing, and performing a most significant bit (MSB) read operation on the memory cells when the voltage of the source line is less than the reference voltage, as the result of the comparing.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged in a row direction and a column direction, a plurality of word lines each connected to memory cells in a row among the memory cells, and a majority of bit lines each connected to memory cells in a column among the memory cells. One or more memory cells are distributed as flag cells among memory cells connected to each word line, and flag cells connected to a first word line and flag cells connected to a second word line that is disposed adjacent to the first word line among the word lines are connected to first and second bit lines, respectively.

Abstract: An integrated circuit includes an internal circuit including a input/output unit suitable for inputting/outputting data, and a voltage supplying circuit suitable for supplying a first operating voltage to the internal circuit in response to a first control signal during a general operation, and supplying a second operating voltage that is higher than the first operating voltage to the input/output unit in response to a second control signal during an output of the data.

Abstract: A semiconductor memory device includes a memory cell part including a main memory unit and a redundancy memory unit, a page buffer circuit including a plurality of page buffer groups and reading data stored in the memory cell part, and a sensing circuit including a plurality of sense amplifiers corresponding to the plurality of page buffer groups, respectively, and suitable for sensing the read data, wherein the plurality of sense amplifiers perform data sensing operations in parallel in order to sense the read data.