Abstract: A nerve probe array has a connector made of a flexible material; and a plurality of probes coupled to the connector, each of the plurality of probe having an electrode formed at a body thereof. The plurality of probes are arranged with intervals in a length direction of the connector, and the connector surrounds an outer circumference of a nerve, and the plurality of probes pierce the outer circumference of the nerve and are inserted into the nerve.

Abstract: The virtual model control system has an input device configured to provide input information for formation, movement or transformation of a virtual model; a control device configured to form the virtual model based on the input information received from the input device, move or transform the virtual model, form a plurality of physical particles at the virtual model, form contact point information therefor, and move the plurality of physical particles to update the contact point information; an output device configured to output the virtual model to the outside. When the plurality of physical particles penetrates into another virtual model in the virtual space, the control devices update the contact point information so that the penetrating physical particles are rearranged at an outer side of the another virtual model.

Abstract: The precise placement device includes: a direction controller to which a placement unit having an insert and a drill is mounted, the direction controller controlling a direction of the placement unit; a precise transfer unit to which the direction controller is mounted, the precise transfer unit transferring the placement unit in the planar two-axis direction; a support table for fixing a target for insertion in which the insert is to be placed; and transfer units for transferring the precise transfer unit and the operating table.

Abstract: A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.

Abstract: A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.

Abstract: A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.

Abstract: Disclosed is a vibration generating method includes providing a vibration generating device which receives a driving power and generates a vibration, and controlling vibration of a vibrator of the vibration generating device, wherein the vibration of the vibrator is controlled by systematizing an inertia matrix and a stiffness matrix of the vibrator, and wherein the inertia matrix and the stiffness matrix simultaneously satisfy diagonalization. A vibration generating device using this method is also disclosed.

Abstract: A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer, etching the hard mask layer to form a first and a second hard mask pattern in the first and the second regions, respectively, reducing a width of the second hard mask pattern formed in the second region and etching the etch target layer using the first hard mask pattern and the second hard mask pattern having the reduced width as an etch barrier to form the etch target patterns in the first and the second regions.

Abstract: A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.

Abstract: The precise placement device includes: a direction controller to which a placement unit having an insert and a drill is mounted, the direction controller controlling a direction of the placement unit; a precise transfer unit to which the direction controller is mounted, the precise transfer unit transferring the placement unit in the planar two-axis direction; a support table for fixing a target for insertion in which the insert is to be placed; and transfer units for transferring the precise transfer unit and the operating table.

Abstract: An etching method in a semiconductor device includes forming a nitride-based first hard mask layer over a target etch layer, forming a carbon-based second hard mask pattern over the first hard mask layer, etching the first hard mask layer using the second hard mask pattern as an etch barrier to form a first hard mask pattern, cleaning a resultant structure including the first hard mask pattern, and etching the target etch layer using the second hard mask pattern as an etch barrier.

Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer having a stack structure of a first insulation layer, a first conductive layer and a second insulation layer over a substrate, forming a recess by etching the sacrificial layer and the substrate, forming a gate insulation layer over a recess surface, filling a second conductive layer in the recess and between etched sacrificial layers, forming a gate electrode metal layer, a gate hard mask layer and a gate mask pattern over a resultant substrate, etching layers formed below the gate mask pattern by using the gate mask pattern until the first conductive layer is exposed, thereby forming an initial gate pattern, forming a capping layer on a sidewall and a top portion of the initial gate pattern, and etching an exposed portion by using the capping layer as a mask until the first insulation layer is exposed, thereby forming a final gate pattern.

Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.

Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.

Abstract: A method for forming a metal pattern in a semiconductor device includes forming an etch stop layer over a semi-finished substrate including a metal layer, forming a hard mask over the etch stop layer, etching the hard mask to form a hard mask pattern exposing the etch stop layer, and etching the etch stop layer and the metal layer using the hard mask pattern.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a tungsten electrode over a substrate, performing a plasma oxidation process to form a capping layer on the surfaces of the gate patterns, forming an etch barrier layer over the substrate where the capping layer is formed, forming an interlayer dielectric layer to fill gap between the gate patterns, and etching the interlayer dielectric layer between the gate patterns to form a contact hole.

Abstract: A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask.

Abstract: A method for fabricating a semiconductor device includes providing a substrate where a cell region and a peripheral region are defined, stacking a conductive layer, a hard mask layer, a metal-based hard mask layer, and an amorphous carbon (C) pattern over the substrate etching the metal-based hard mask layer using the amorphous C pattern as an etch mask, thereby forming a resultant structure, forming a photoresist pattern covering the resultant structure in the cell region while exposing the resultant structure in the peripheral region, decreasing a width of the etched metal-based hard mask layer in the peripheral region, removing the photoresist pattern and the amorphous C pattern, and forming a conductive pattern by etching the hard mask layer and the conductive layer using the etched metal-based hard mask layer as an etch mask.

Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer having a stack structure of a first insulation layer, a first conductive layer and a second insulation layer over a substrate, forming a recess by etching the sacrificial layer and the substrate, forming a gate insulation layer over a recess surface, filling a second conductive layer in the recess and between etched sacrificial layers, forming a gate electrode metal layer, a gate hard mask layer and a gate mask pattern over a resultant substrate, etching layers formed below the gate mask pattern by using the gate mask pattern until the first conductive layer is exposed, thereby forming an initial gate pattern, forming a capping layer on a sidewall and a top portion of the initial gate pattern, and etching an exposed portion by using the capping layer as a mask until the first insulation layer is exposed, thereby forming a final gate pattern.

Abstract: A method for forming a gate electrode in a semiconductor device includes providing a substrate, forming a gate insulation layer over the substrate, forming first and second conductive layers over the gate insulation layer, forming a hard mask pattern over the second conductive layer, etching the second conductive layer using the hard mask pattern as an etch mask, performing an oxidation process to form an anti-oxidation layer on a sidewall of the etched second conductive layer, and etching the first conductive layer using the hard mask as an etch mask.