Abstract: A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided from an external test device to generate an internal clock signal having a relatively high frequency. The data input buffer buffers test pattern data provided in synchronization to the external clock signal to output the buffered test pattern data. The test data generator generates test data that is to be synchronized to the internal clock signal, using the outputted test pattern data based on a first or a second control signal. The data output buffer outputs the generated test data to a memory core of the semiconductor memory device. The test device generates various test data suitable for a memory test at a high operating speed.

Abstract: In a method of generating an internal clock for a semiconductor memory device, a doubled clock is generated during operation in a high-speed test mode in response to an external clock. A data clock is generated by delaying the doubled clock so that data read from a memory cell array in the semiconductor memory device is output in synchronization with the external clock. A doubled sync clock synchronized with the external clock is generated by delaying the data clock. An internal clock is generated during operation in the high-speed test mode by delaying the doubled sync clock by a delay amount that corresponds to a delay amount experienced in generation of an internal clock in response to the external clock during operation in a normal mode. Accordingly, the high-speed test operation of the semiconductor memory device can be efficiently performed.

Abstract: An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled data. The data pattern setting circuit sets a pattern of the second data responsive to a test mode signal and a data pattern select signal to generate third data. Accordingly, the semiconductor memory device including the input circuit may generate data of various patterns in a test mode, and may perform a high-speed test using a low-speed tester.

Abstract: A semiconductor memory device is tested responsive to an output clock signal. Parallel test data in the semiconductor memory device are generated and a plurality of data output clock signals are generated by selectively activating one of the data output clock signals according to a test mode. The parallel test data are respectively applied to a plurality of output circuits and one of the output circuits is activated responsive to the activated data output clock signal. The parallel test data transferred through the activated output circuit are serialized and the serialized data are output responsive to the output clock signal. Therefore, the semiconductor memory device is tested without loss of a valid data output time.

Abstract: A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver.

Abstract: A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.

Abstract: A CMOS inverter cell having a small horizontal length which is reduced by substituting metal lines for supplying data signals to gates with a connection pattern which is mounted in one end of a supply voltage area of the CMOS inverter cell and is made of the same material as the gate. Data is supplied to the gates through at least one side of the CMOS inverter cell. A single gate pattern or a plurality of different gate patterns may be used.

Abstract: A pad layout structure may include a pad and adjacent circuit areas having an electrostatic protection circuit and a data input/output circuit. The pad may be selectively connected to the adjacent circuit areas depending on the intended use of the pad.

Abstract: In a method of generating an internal clock for a semiconductor memory device, a doubled clock is generated during operation in a high-speed test mode in response to an external clock. A data clock is generated by delaying the doubled clock so that data read from a memory cell array in the semiconductor memory device is output in synchronization with the external clock. A doubled sync clock synchronized with the external clock is generated by delaying the data clock. An internal clock is generated during operation in the high-speed test mode by delaying the doubled sync clock by a delay amount that corresponds to a delay amount experienced in generation of an internal clock in response to the external clock during operation in a normal mode. Accordingly, the high-speed test operation of the semiconductor memory device can be efficiently performed.

Abstract: A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided from an external test device to generate an internal clock signal having a relatively high frequency. The data input buffer buffers test pattern data provided in synchronization to the external clock signal to output the buffered test pattern data. The test data generator generates test data that is to be synchronized to the internal clock signal, using the outputted test pattern data based on a first or a second control signal. The data output buffer outputs the generated test data to a memory core of the semiconductor memory device. The test device generates various test data suitable for a memory test at a high operating speed.

Abstract: Delayed locked loop (DLL) circuits and methods using a coarse-fine lock structure which prevent malfunction due to jitter or noise that causes erroneous transitions from a coarse-lock to a fine-lock delay. A phase detector uses two feedback signals to detect a phase of an external clock signal (or reference signal) based on a phase difference between the two feedback signals, thereby enabling a more accurate determination as to when to transition from a coarse-lock to a fine-lock delay. The phase difference of the two feedback signals can be regulated by using frequency information to set a phase difference between the first and second feedback signals to renders the detection process more robust against noise or jitter over a wide frequency band from a low frequency to a high frequency, for determining when to transition from the coarse-lock to the fine-lock.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.

Abstract: A delay locked loop (DLL) is provided that includes a phase detector configured to detect a phase error between an internal clock signal and the external clock signal and output a phase error signal. A low pass filter is configured to output a predetermined control signal in response to the phase error signal. A variable delay circuit is configured to change a delay time in response to the predetermined control signal, delay the phase of the external clock signal with respect to the changed delay time, lock the delayed external clock signal and output the internal clock signal. A compensation delay circuit is configured to receive a control voltage based on a delay time introduced by a data output circuit and delay a phase of the internal clock signal for a first delay time based on the control voltage and output the delayed internal clock signal to the phase detector. Methods of compensating a delay for a DLL are also provided.

Abstract: A synchronous semiconductor memory device includes an output control signal generating circuit that generates a data output control signal in response to an internal clock signal, an output control clock signal and a CAS latency signal. The output control signal generating circuit successively shifts read information signals in response to the internal clock signal and the output control clock signal, both source clocks of which are identical, and generates one of the shifted read information signals as an output control signal for indicating a data output period in response to the CAS latency signal. The synchronous semiconductor memory device can synchronize the source clocks of the clock signals used in the output control signal generating circuit thereby reducing the influence of clock jitter.

Abstract: An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

Abstract: Delayed locked loop (DLL) circuits and methods using a coarse-fine lock structure are provided, which prevent malfunction due to jitter or noise that causes erroneous transitions form a coarse-lock to a fine-lock delay. A phase detector uses two feedback signals to detect a phase of an external clock signal (or reference signal) based on a phase difference between the two feedback signals, thereby enabling a more accurate determination as to when to transition from a coarse-lock to a fine-lock delay. The phase difference of the two feedback signals can be regulated by using frequency information to set a phase difference between the first and second feedback signals to renders the detection process more robust against noise or jitter over a wide frequency band from a low frequency to a high frequency, for determining when to transition from the coarse-lock to the fine-lock.

Abstract: An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

Abstract: An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

Abstract: A delay locked loop (DLL) is provided that includes a phase detector configured to detect a phase error between an internal clock signal and the external clock signal and output a phase error signal. A low pass filter is configured to output a predetermined control signal in response to the phase error signal. A variable delay circuit is configured to change a delay time in response to the predetermined control signal, delay the phase of the external clock signal with respect to the changed delay time, lock the delayed external clock signal and output the internal clock signal. A compensation delay circuit is configured to receive a control voltage based on a delay time introduced by a data output circuit and delay a phase of the internal clock signal for a first delay time based on the control voltage and output the delayed internal clock signal to the phase detector. Methods of compensating a delay for a DLL are also provided.

Abstract: A synchronous semiconductor memory device includes an output control signal generating circuit that generates a data output control signal in response to an internal clock signal, an output control clock signal and a CAS latency signal. The output control signal generating circuit successively shifts read information signals in response to the internal clock signal and the output control clock signal, both source clocks of which are identical, and generates one of the shifted read information signals as an output control signal for indicating a data output period in response to the CAS latency signal. The synchronous semiconductor memory device can synchronize the source clocks of the clock signals used in the output control signal generating circuit thereby reducing the influence of clock jitter.