Abstract: Integrated circuit devices having signal buffers therein include first and second storage devices that are electrically coupled in series and configured so that data can be loaded into the first storage device in-sync with a first clock signal (e.g., external clock signal) and then passed and loaded into the second storage device in-sync with a second clock signal (e.g., internal clock signal). The second clock signal is derived from the first clock signal and may be a delayed version of the first clock signal having an equivalent duty cycle. The buffer also comprises an integrated circuit that operates synchronously with the second clock signal and a transfer device that passes an output of the second storage device to the integrated circuit in-sync with the second clock signal. In this manner, data can be loaded into the integrated circuit in-sync with the same clock signal used to control the integrated circuit even though the data is originally transferred in-sync with another clock signal.

Abstract: An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

Abstract: Integrated circuit memory devices according to the present invention include a current sense amplifier having first and second cross-coupled sensing transistors. First and second data lines are electrically coupled to the source of the first sensing transistor and the source of the second sensing transistor, respectively. The current sense amplifier includes a first load transistor that has a source electrically connected to a drain of the first sensing transistor and a gate of the second sensing transistor and a second load transistor is included that has a source electrically connected to a drain of the second sensing transistor and a gate of the first sensing transistor. A switching transistor is responsive to an enable signal and has a source electrically coupled to a drain of the first load transistor and a drain of said second load transistor. A first load circuit provides a variable impedance across the source and the drain of the first load transistor in response to at least a first sense signal.

Abstract: Integrated circuit memory devices according to the present invention include a current sense amplifier having first and second cross-coupled sensing transistors. First and second data lines are electrically coupled to the source of the first sensing transistor and the source of the second sensing transistor, respectively. The current sense amplifier includes a first load transistor that has a source electrically connected to a drain of the first sensing transistor and a gate of the second sensing transistor and a second load transistor is included that has a source electrically connected to a drain of the second sensing transistor and a gate of the first sensing transistor. A switching transistor is responsive to an enable signal and has a source electrically coupled to a drain of the first load transistor and a drain of said second load transistor. A first load circuit provides a variable impedance across the source and the drain of the first load transistor in response to at least a first sense signal.

Abstract: A power control circuit controls a voltage supplied to a load circuit, such as a memory write driver circuit, that exhibits a current demand responsive to a load control signal applied thereto. The power control circuit includes a power supply input terminal configured to receive a supply voltage and an output terminal configured to connect to the load circuit. A voltage regulator circuit is connected between the power supply input terminal and the output terminal and operative to regulate a voltage at the output terminal. A bypass circuit is operative to couple the power supply input terminal to the output terminal responsive to the load control signal and thereby bypass the voltage regulator circuit. The bypass circuit preferably includes a bypass control circuit configured to receive the load control signal and operative to generate a bypass control signal responsive to the load control signal, and a switching circuit, e.g.