Patents by Inventor Sang-Yeon Han
Sang-Yeon Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200150377Abstract: The present embodiment relates to a camera module comprising: a bobbin, which has a through-hole formed therein; a lens module, which is accommodated in the through-hole and is coupled to the bobbin; a protrusion formed to protrude from the outer peripheral surface of the lens module; and a recess formed to be recessed from the inner peripheral surface of the bobbin so as to accommodate at least a part of the protrusion, wherein the recess comprises a first guide portion, which extends downwards from the upper end of the bobbin, and a second guide portion, which extends so as to slope from the first guide portion.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Sang Yeon HAN, Young Taek OH
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Patent number: 10571643Abstract: The present embodiment relates to a camera module comprising: a bobbin, which has a through-hole formed therein; a lens module, which is accommodated in the through-hole and is coupled to the bobbin; a protrusion formed to protrude from the outer peripheral surface of the lens module; and a recess formed to be recessed from the inner peripheral surface of the bobbin so as to accommodate at least a part of the protrusion, wherein the recess comprises a first guide portion, which extends downwards from the upper end of the bobbin, and a second guide portion, which extends so as to slope from the first guide portion.Type: GrantFiled: July 7, 2016Date of Patent: February 25, 2020Assignee: LG INNOTEK CO., LTD.Inventors: Sang Yeon Han, Young Taek Oh
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Publication number: 20180329277Abstract: One embodiment of a camera module comprises: a lens barrel including at least one lens; a bobbin for accommodating the lens barrel; and a fixing part disposed between the lens barrel and the bobbin so as to inhibit the lens barrel from being separated from the bobbin, wherein one surface, which makes surface contact with the fixing part, of the bobbin can include a bobbin provided so as to protrude toward the lens barrel.Type: ApplicationFiled: November 2, 2016Publication date: November 15, 2018Inventors: SANG YEON HAN, DO YUN KIM, JUNG HWAN KIM, YONG NAM CHOI
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Publication number: 20180217348Abstract: The present embodiment relates to a camera module comprising: a bobbin, which has a through-hole formed therein; a lens module, which is accommodated in the through-hole and is coupled to the bobbin; a protrusion formed to protrude from the outer peripheral surface of the lens module; and a recess formed to be recessed from the inner peripheral surface of the bobbin so as to accommodate at least a part of the protrusion, wherein the recess comprises a first guide portion, which extends downwards from the upper end of the bobbin, and a second guide portion, which extends so as to slope from the first guide portion.Type: ApplicationFiled: July 7, 2016Publication date: August 2, 2018Inventors: Sang Yeon Han, Young Taek Oh
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Publication number: 20180196219Abstract: The present embodiments relate to a dual camera module comprising: a first camera module including a first lens module and a first image sensor disposed below the first lens module; and a second camera module including a second lens module and a second image sensor disposed below the second lens module, wherein the second camera module has a wider angle of view than the first camera module, and the second image sensor is disposed at a position higher than the first image sensor.Type: ApplicationFiled: June 24, 2016Publication date: July 12, 2018Inventors: Young Don O, Sang Yeon HAN
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Publication number: 20160322354Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.Type: ApplicationFiled: July 13, 2016Publication date: November 3, 2016Inventors: Kyo-Suk CHAE, Satoru YAMADA, Sang-Yeon HAN, Young-Jin CHOI, Wook-Je KIM
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Patent number: 9418988Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.Type: GrantFiled: August 15, 2014Date of Patent: August 16, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-Suk Chae, Satoru Yamada, Sang-Yeon Han, Young-Jin Choi, Wook-Je Kim
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Patent number: 8823113Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.Type: GrantFiled: January 5, 2011Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-Suk Chae, Satoru Yamada, Sang-Yeon Han, Young-Jin Choi, Wook-Je Kim
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Publication number: 20120001271Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.Type: ApplicationFiled: January 5, 2011Publication date: January 5, 2012Inventors: Kyo-Suk Chae, Satoru Yamada, Sang-Yeon Han, Young-Jin Choi, Wook-Je Kim
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Patent number: 7936021Abstract: In a fin field effect transistor (Fin FET) and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.Type: GrantFiled: October 23, 2007Date of Patent: May 3, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hoon Jeon, Satoru Yamada, Sang-Yeon Han, Jong-Man Park, Si-Ok Sohn
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Patent number: 7795678Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions.Type: GrantFiled: June 12, 2008Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Man Park, Satoru Yanada, Sang-Yeon Han, Jun-Bum Lee, Si-Ok Sohn
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Patent number: 7560759Abstract: A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.Type: GrantFiled: December 13, 2006Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Soo Kang, Jae-Man Yoon, Dong-Gun Park, Sang-Yeon Han, Young-Joon Ahn, Choong-Ho Lee
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Publication number: 20080308863Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions.Type: ApplicationFiled: June 12, 2008Publication date: December 18, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Man PARK, Satoru YANADA, Sang-Yeon HAN, Jun-Bum LEE, Si-Ok SOHN
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Publication number: 20080099850Abstract: In a fin field effect transistor (Fin FET)and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.Type: ApplicationFiled: October 23, 2007Publication date: May 1, 2008Inventors: Chang-Hoon Jeon, Satoru Yamada, Sang-Yeon Han, Jong-Man Park, Si-Ok Sohn
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Patent number: 7358142Abstract: A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.Type: GrantFiled: January 28, 2005Date of Patent: April 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Soo Kang, Chul Lee, Tae-Yong Kim, Dong-Gun Park, Young-Joon Ahn, Choong-Ho Lee, Sang-Yeon Han
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Patent number: 7265011Abstract: A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.Type: GrantFiled: July 22, 2004Date of Patent: September 4, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Man Yoon, Dong-gun Park, Makoto Yoshida, Gyo-Young Jin, Jeong-dong Choe, Sang-Yeon Han
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Publication number: 20070085127Abstract: A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.Type: ApplicationFiled: December 13, 2006Publication date: April 19, 2007Inventors: Hee-Soo Kang, Jae-Man Yoon, Dong-Gun Park, Sang-Yeon Han, Young-Joon Ahn, Choong-Ho Lee
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Patent number: 7166514Abstract: A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.Type: GrantFiled: February 1, 2005Date of Patent: January 23, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Soo Kang, Jae-Man Yoon, Dong-Gun Park, Sang-Yeon Han, Young-Joon Ahn, Choong-Ho Lee
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Publication number: 20050170593Abstract: A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.Type: ApplicationFiled: January 28, 2005Publication date: August 4, 2005Inventors: Hee-Soo Kang, Chul Lee, Tae-Yong Kim, Dong-Gun Park, Young-Joon Ahn, Choong-Ho Lee, Sang-Yeon Han
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Publication number: 20050167754Abstract: A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.Type: ApplicationFiled: February 1, 2005Publication date: August 4, 2005Inventors: Hee-Soo Kang, Jae-Man Yoon, Dong-Gun Park, Sang-Yeon Han, Young-Joon Ahn, Choong-Ho Lee