Patents by Inventor Sang-Yeon Han

Sang-Yeon Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050048729
    Abstract: A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.
    Type: Application
    Filed: July 22, 2004
    Publication date: March 3, 2005
    Inventors: Jae-Man Yoon, Dong-gun Park, Makoto Yoshida, Gyo-Young Jin, Jeong-dong Choe, Sang-Yeon Han
  • Patent number: 6680224
    Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: January 20, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-cheol Shin, Jong-ho Lee, Sang-yeon Han
  • Publication number: 20030132466
    Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.
    Type: Application
    Filed: March 17, 2003
    Publication date: July 17, 2003
    Inventors: Hyung-Cheol Shin, Jong-Ho Lee, Sang-Yeon Han
  • Patent number: 6563151
    Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: May 13, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-cheol Shin, Jong-ho Lee, Sang-yeon Han
  • Publication number: 20020028546
    Abstract: Disclosed is a method of fabricating an MOS transistor. The method comprises the following steps of: forming a gate pattern having a gate insulation film, main gate and a capping layer which are sequentially layered on a p-type semiconductor substrate; forming an isolating insulation film on the whole surface of a resultant structure having the gate pattern; forming a material layer for side gate on the isolating insulation film, the material layer having a work function smaller than those of the semiconductor substrate and the main gate; anisotropically etching the material layer for side gate and the isolating insulation film till the semiconductor substrate and the capping layer are exposed to form an isolating insulation pattern and side gate; respectively forming an n-type source/drain; and forming a conductive film pattern on the resultant structure, the conductive film electrically connecting the source to the adjacent side gate or the drain to the adjacent side gate.
    Type: Application
    Filed: September 4, 2001
    Publication date: March 7, 2002
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Hyung Cheol Shin, Jong Ho Lee, Sang Yeon Han, Sung Il Chang