Abstract: The present disclosure relates to methods of detecting a protein from the SARS-CoV-2 virus, or a fragment thereof, in a sample obtained from a subject using a first antibody or antigen-binding fragment thereof that binds to a protein from the SARS-CoV-2 virus, or a fragment thereof, and a second antibody or antigen-binding fragment thereof which binds to a protein from the SARS-CoV-2 virus, or a fragment thereof.

Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

Abstract: A system and method are configured to supply parts for use in a vehicle manufacturing process. The vehicle parts supply system includes a parts loading device in which a plurality of parts is loaded, a scanning device configured to scan the plurality of parts loaded in the parts loading device, a controller configured to select one or more parts having a specification suitable for a manufacturing target vehicle among the plurality of parts loaded in the parts loading device from a scanned image by the scanning device, and a pick and place device configured to move and align the parts selected by the controller from the parts loading device to a parts alignment device.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: The present disclosure relates to methods of detecting a protein from the SARS-CoV-2 virus, or a fragment thereof, in a sample obtained from a subject using a first antibody or antigen-binding fragment thereof that binds to a protein from the SARS-CoV-2 virus, or a fragment thereof, and a second antibody or antigen-binding fragment thereof which binds to a protein from the SARS-CoV-2 virus, or a fragment thereof.

Abstract: A semiconductor package is provided. The semiconductor package can include a first redistributed layer on which a plurality of semiconductor chips and a plurality of passive devices are mounted on one surface, a second redistributed layer electrically connected to the first redistributed layer through a via, an external connection terminal formed on the lower surface of the second redistributed layer, a first mold provided to cover the plurality of semiconductor chips and the plurality of passive devices on the first redistributed layer, and a second mold provided between the first redistributed layer and the second redistributed layer. Each of the first redistributed layer and the second redistributed layer includes a wiring pattern and an insulating layer and is composed of a plurality of layers, and at least one of the plurality of semiconductor chips is disposed between the first redistributed layer and the second redistributed layer.

Abstract: A semiconductor device includes a substrate. A first channel pattern is disposed on the substrate. The first channel pattern includes a first side and a second side opposite to each other in a first direction. A first gate electrode is disposed on the first side of the first channel pattern. A first source/drain electrode is disposed on the first side of the first channel pattern. A second source/drain electrode is disposed on the second side of the first channel pattern. The first gate electrode overlaps the second source/drain electrode in the first direction.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

Abstract: Disclosed are methods of forming PN junction structures, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated by the same. The method of forming a PN junction structure includes: forming on a substrate a first material layer that includes first transition metal atoms and first chalcogen atoms, loading the first material layer into a process chamber and supplying a gas of second chalcogen atoms, and forming a second material layer by substituting the second chalcogen atoms for the first chalcogen atoms on a selected portion of the first material layer. The first material layer has one of n-type conductivity and p-type conductivity. The second material layer has the other of the n-type conductivity and the p-type conductivity.

Abstract: A foldable display set may include: a foldable display device; and a holding system on a rear surface of the foldable display device and configured to fold and unfold the foldable display device. The holding system may include: a motor configured to generate a rotational force; a rotational arm configured to be rotated by the rotational force of the motor to fold and unfold the foldable display device; a fixing plate spaced apart from the rotational arm with the foldable display device in an unfolded state; a moving plate on the fixing plate and configured to be moved with respect to the fixing plate by the rotational arm; and a magnetic unit fixed on the moving plate. The foldable display device in a folded state may be fixed to the magnetic unit via a magnetic force.

Abstract: The present disclosure relates to a unit chair.

Abstract: Provided are a compound represented by Formula 1 or Formula A, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode and an electronic device thereof, wherein the compound represented by Formula 1 or Formula A is included in the organic material layer, and thereby the driving voltage of the organic electronic device can be lowered, and the luminous efficiency and life time of the organic electronic device can be improved.

Abstract: Provided are a compound represented by Formula 24, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode and comprising the compound of Formula 24, and an electronic device thereof, the element and device having improved driving voltage, luminous efficiency and life time from the employment of the compound.

Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: The present disclosure relates to methods of detecting a protein from the SARS-CoV-2 virus, or a fragment thereof, in a sample obtained from a subject using a first antibody or antigen-binding fragment thereof that binds to a protein from the SARS-CoV-2 virus, or a fragment thereof, and a second antibody or antigen-binding fragment thereof which binds to a protein from the SARS-CoV-2 virus, or a fragment thereof.

Abstract: A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.

Abstract: A semiconductor package is provided. The semiconductor package can include a first redistributed layer on which a plurality of semiconductor chips and a plurality of passive devices are mounted on one surface, a second redistributed layer electrically connected to the first redistributed layer through a via, an external connection terminal formed on the lower surface of the second redistributed layer, a first mold provided to cover the plurality of semiconductor chips and the plurality of passive devices on the first redistributed layer, and a second mold provided between the first redistributed layer and the second redistributed layer. Each of the first redistributed layer and the second redistributed layer includes a wiring pattern and an insulating layer and is composed of a plurality of layers, and at least one of the plurality of semiconductor chips is disposed between the first redistributed layer and the second redistributed layer.