Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

Abstract: The present invention provides the compound represented by Formula 1 or Formula A, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and electronic device thereof, and by comprising the compound represented by Formula 1 or Formula A in the organic material layer, the driving voltage of the organic electronic device can be lowered, and the luminous efficiency and life time of the organic electronic device can be improved.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

Abstract: A superconducting arcing induction type DC circuit breaker includes a superconducting fault current limiter and an arcing induction type DC circuit breaker connected in series to each other. The arcing induction type DC circuit breaker includes an induction member that has a through-hole, is continuously formed in a 360-degree direction, and has a certain shape and thickness, and an induction needle that protrudes from an inner surface of the induction member toward a center of the induction member. A contact point where an anode and a cathode, which are mechanical contacts, approach from opposite directions and come into contact with each other is formed in the through-hole of the induction member, and the anode and the cathode are separated in a direction far away from each other.

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

Abstract: Disclosed is a method for bi-directional calling between an open system module and a mainframe system module, which is performed in a computing device including one or more processors and a main memory storing commands executable in the processors. The method may include: receiving, by a front-end interface, a calling for a mainframe function on the mainframe system module from the open system module program; requesting, by an entrance point processing unit of the front-end interface, information on the mainframe function to a program processing unit of a back-end interface; controlling, by the entrance point processing unit of the front-end interface, a register processing unit of the back-end interface to set a mainframe register value used in the mainframe system module; and transferring, by the front-end interface, a system control to the mainframe system module through a control transfer processing unit of the back-end interface so as to drive the mainframe function on the mainframe system module.

Abstract: The present disclosure relates to a method and device for controlling a Downlink Data Notification (DDN) message, which can reduce the DDN messages that occur while a user equipment transits from an active (ECM-active) state to an inactive (ECM-idle) state. During a bearer activation procedure according to a request from a user equipment, the DDN message control apparatus of the present disclosure sets a DDN flag value to a predetermined value when uplink data is received. When a DDN message is received from outside, the apparatus identifies the DDN flag value and stores the DDN message in case that the DDN flag value is identical with the predetermined value.

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

Abstract: Disclosed is a method for bi-directional calling between an open system module and a mainframe system module, which is performed in a computing device including one or more processors and a main memory storing commands executable in the processors. The method may include: receiving, by a front-end interface, a calling for a mainframe function on the mainframe system module from the open system module program; requesting, by an entrance point processing unit of the front-end interface, information on the mainframe function to a program processing unit of a back-end interface; controlling, by the entrance point processing unit of the front-end interface, a register processing unit of the back-end interface to set a mainframe register value used in the mainframe system module; and transferring, by the front-end interface, a system control to the mainframe system module through a control transfer processing unit of the back-end interface so as to drive the mainframe function on the mainframe system module.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: A superconducting arcing induction type DC circuit breaker includes a superconducting fault current limiter and an arcing induction type DC circuit breaker connected in series to each other. The arcing induction type DC circuit breaker includes an induction member that has a through-hole, is continuously formed in a 360-degree direction, and has a certain shape and thickness, and an induction needle that protrudes from an inner surface of the induction member toward a center of the induction member. A contact point where an anode and a cathode, which are mechanical contacts, approach from opposite directions and come into contact with each other is formed in the through-hole of the induction member, and the anode and the cathode are separated in a direction far away from each other.