Patents by Inventor Sanghoon BAEK
Sanghoon BAEK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088039Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jungho DO, Sanghoon BAEK
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Patent number: 11854976Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.Type: GrantFiled: May 10, 2022Date of Patent: December 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sanghoon Baek, Seung Young Lee
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Patent number: 11842964Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.Type: GrantFiled: May 18, 2021Date of Patent: December 12, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jungho Do, Sanghoon Baek
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Patent number: 11810920Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.Type: GrantFiled: September 21, 2020Date of Patent: November 7, 2023Inventors: Ji Su Yu, Jae-Ho Park, Sanghoon Baek, Hyeon Gyu You, Seung Young Lee, Seung Man Lim
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Publication number: 20230335559Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon BAEK, Jungho DO, Jaewoo SEO, Jisu YU
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Publication number: 20230307436Abstract: An integrated circuit may include a first function cell and a second function cell each corresponding to a first circuit, wherein the first function cell may include a first pattern extending in a first direction along a first grid in a first layer and a second pattern extending in the first direction along a second grid in a second layer, the first grid may have a first pitch greater than a second pitch of the second grid in a second direction crossing the first direction, and the second function cell may include a layout of the first function cell and have a length greater than a length of the first function cell by the first pitch in the second direction.Type: ApplicationFiled: March 17, 2023Publication date: September 28, 2023Inventors: Jungho Do, Taejoong Song, Sanghoon Baek, Jisu Yu, Hyeongyu You, Minjae Jeong, Jonghoon Jung
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Publication number: 20230297752Abstract: Integrated circuits including abutted blocks and methods of designing layouts of the integrated circuits are disclosed. The integrated circuit includes a first block having a first function cell array therein, which is at least partially surrounded by a first plurality of finishing cells, and a second block extending adjacent the first block. The second block includes a second function cell array therein, which is at least partially surrounded by a second plurality of finishing cells. The first plurality of finishing cells include: (i) a first finishing cell placed at a boundary of the integrated circuit, and (ii) a second finishing cell different from the first finishing cell, which is placed at a boundary between the first block and the second block.Type: ApplicationFiled: January 31, 2023Publication date: September 21, 2023Inventors: Jungho Do, Jisu Yu, Hyeongyu You, Minjae Jeong, Sanghoon Baek
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Patent number: 11764201Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.Type: GrantFiled: January 26, 2021Date of Patent: September 19, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Su Yu, Jae-Woo Seo, Sanghoon Baek, Hyeon Gyu You
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Publication number: 20230290783Abstract: A semiconductor device includes a substrate including an N-stack cell, a buffer cell and an M-stack cell that are on the substrate, the buffer cell being between the N-stack and M-stack cells, an active pattern extending from the N-stack cell to the M-stack cell via the buffer cell, an N-stack channel pattern on the active pattern of the N-stack cell, an M-stack channel pattern on the active pattern of the M-stack cell, a dummy channel pattern on the active pattern of the buffer cell, an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern, and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern. The N-stack channel pattern includes stacked N semiconductor patterns. The M-stack channel pattern includes stacked M semiconductor patterns. Each of N and M is an integer number of 2 or more, and M is greater than N.Type: ApplicationFiled: November 29, 2022Publication date: September 14, 2023Inventors: Jeongsoon Kong, Myung Gil Kang, Sanghoon Baek
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Patent number: 11755809Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.Type: GrantFiled: August 27, 2021Date of Patent: September 12, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jisu Yu, Jaewoo Seo, Hyeongyu You, Sanghoon Baek, Jonghoon Jung
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Patent number: 11705456Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.Type: GrantFiled: March 12, 2021Date of Patent: July 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon Baek, Jungho Do, Jaewoo Seo, Jisu Yu
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Patent number: 11695002Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.Type: GrantFiled: April 13, 2022Date of Patent: July 4, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon Baek, Myung Gil Kang, Jae-Ho Park, Seung Young Lee
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Patent number: 11626516Abstract: Provided is an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells, wherein a distance between a pair of second vertical channel structures of a first cell and an adjacent pair of first vertical channel structures in a second cell, all facing a cell boundary between the first and second cells, is the same as a distance between the pair of the first vertical channel structures and a pair of second vertical channel structures arranged next to the pair of the first vertical channel structures in the first cell.Type: GrantFiled: December 30, 2020Date of Patent: April 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon Baek, Jeong Soon Kong, Jung Ho Do
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Publication number: 20220344463Abstract: An integrated circuit may include a first cell and a second cell. The first cell includes a first transistor in which nanosheets included in a first nanosheet stack and a second nanosheet stack extend in a first direction to pass through a first gate electrode that extends in a second direction intersecting with the first direction. The second cell includes a second transistor in which one or more nanosheets included in a third nanosheet stack extends in the first direction to pass through a second gate electrode that extends in the second direction. A length of the first cell in the second direction may be greater than a length of the second cell in the second direction.Type: ApplicationFiled: April 13, 2022Publication date: October 27, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hakchul Jung, Myunggil Kang, Jungho Do, Sanghoon Baek
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Publication number: 20220328408Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.Type: ApplicationFiled: November 22, 2021Publication date: October 13, 2022Inventors: Jungho Do, Sanghoon Baek
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Patent number: 11462475Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.Type: GrantFiled: June 24, 2020Date of Patent: October 4, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sanghoon Baek, Seung Young Lee
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Publication number: 20220302131Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.Type: ApplicationFiled: June 3, 2022Publication date: September 22, 2022Inventors: JUNG-HO DO, SEUNGYOUNG LEE, JONGHOON JUNG, JINYOUNG LIM, GIYOUNG YANG, SANGHOON BAEK, TAEJOONG SONG
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Publication number: 20220300693Abstract: An integrated circuit includes a first cell including a first lower pattern extending in a first direction along a first track in a first wiring layer; and a second cell including a second lower pattern that extends in the first direction along the first track in the first wiring layer, and is a minimum space of the first wiring layer or farther apart from the first lower pattern, wherein the first lower pattern corresponds to a pin of the first cell, and the second lower pattern is farther apart from a boundary between the first cell and the second cell than the first lower pattern is.Type: ApplicationFiled: February 11, 2022Publication date: September 22, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jungho DO, Jaewoo SEO, Sanghoon BAEK, Jisu YU, Hyeongyu YOU, Minjae JEONG
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Publication number: 20220270969Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.Type: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sanghoon BAEK, Seung Young LEE
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Patent number: RE49780Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.Type: GrantFiled: June 30, 2020Date of Patent: January 2, 2024Inventors: Taejoong Song, Sanghoon Baek, Sungwe Cho, Jung-Ho Do, Giyoung Yang, Jinyoung Lim