Patents by Inventor Sanjay Natarajan
Sanjay Natarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11749315Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: GrantFiled: December 15, 2021Date of Patent: September 5, 2023Assignee: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
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Patent number: 11705335Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.Type: GrantFiled: April 20, 2022Date of Patent: July 18, 2023Assignee: Applied Materials, Inc.Inventors: Srinivas Gandikota, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy, Gaurav Thareja, Mukund Srinivasan, Sanjay Natarajan
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Patent number: 11682668Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.Type: GrantFiled: October 13, 2021Date of Patent: June 20, 2023Assignee: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Sanjay Natarajan
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Patent number: 11621266Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.Type: GrantFiled: November 9, 2021Date of Patent: April 4, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
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Publication number: 20230039074Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: Michael Stolfi, Myungsun Kim, Benjamin Colombeau, Sanjay Natarajan
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Patent number: 11508828Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.Type: GrantFiled: June 22, 2021Date of Patent: November 22, 2022Assignee: Applied Materials, Inc.Inventors: Michael Stolfi, Myungsun Kim, Benjamin Colombeau, Sanjay Natarajan
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Publication number: 20220367270Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Micromaterials LLCInventors: Yuriy Shusterman, Madhur Sachan, Susmit Singha Roy, Regina Freed, Sanjay Natarajan
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Patent number: 11462411Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: GrantFiled: April 28, 2021Date of Patent: October 4, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Gaurav Thareja, Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sanjay Natarajan, Sean M. Seutter, Dong Wu
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Patent number: 11437273Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.Type: GrantFiled: February 24, 2020Date of Patent: September 6, 2022Assignee: Micromaterials LLCInventors: Yuriy Shusterman, Madhur Sachan, Susmit Singha Roy, Regina Freed, Sanjay Natarajan
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Publication number: 20220246432Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Srinivas Gandikota, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy, Gaurav Thareja, Mukund Srinivasan, Sanjay Natarajan
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Publication number: 20220199804Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Applicant: Applied Materials, Inc.Inventors: Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer, Dimitri R. Kioussis, Sanjay Natarajan, Abhishek Dube
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Patent number: 11328928Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.Type: GrantFiled: June 18, 2019Date of Patent: May 10, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Srinivas Gandikota, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy, Gaurav Thareja, Mukund Srinivasan, Sanjay Natarajan
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Publication number: 20220130722Abstract: A substrate processing method includes creating a mask on a top surface of a workpiece. A first portion of a gap fill material is overlaid by the mask and a second portion of the gap fill material is exposed through an opening in the mask. The method further includes exposing the workpiece to a plasma. The method further includes performing a first etching of the first portion of the gap fill material to create a first cavity while the second portion of the gap fill material remains in place, depositing a first metal-containing substance in the first cavity, performing a second etching of the second portion of the gap fill material to create a second cavity while the first metal-containing substance remains in place, and depositing a second metal-containing substance in the second cavity.Type: ApplicationFiled: October 19, 2021Publication date: April 28, 2022Inventors: Suketu Arun PARIKH, Martin Jay SEAMONS, Jingmei LIANG, Shuchi Sunil OJHA, Tom CHOI, Nitin K. INGLE, Sanjay NATARAJAN
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Patent number: 11309404Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.Type: GrantFiled: July 3, 2019Date of Patent: April 19, 2022Assignee: Applied Materials, Inc.Inventors: Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer, Dimitri R. Kioussis, Sanjay Natarajan, Abhishek Dube
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Publication number: 20220108728Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
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Patent number: 11295786Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: GrantFiled: February 3, 2020Date of Patent: April 5, 2022Assignee: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
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Publication number: 20220093749Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.Type: ApplicationFiled: December 3, 2021Publication date: March 24, 2022Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Tushar Vidyadhar MANDREKAR, Yuan-hui LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
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Publication number: 20220068935Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.Type: ApplicationFiled: November 9, 2021Publication date: March 3, 2022Applicant: Applied Materials, Inc.Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
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Publication number: 20220068917Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.Type: ApplicationFiled: October 13, 2021Publication date: March 3, 2022Applicant: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Sanjay Natarajan
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Publication number: 20220013624Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.Type: ApplicationFiled: September 28, 2021Publication date: January 13, 2022Applicant: Micromaterials LLCInventors: Uday Mitra, Regina Freed, Ho-yung David Hwang, Sanjay Natarajan, Lequn Liu