Patents by Inventor Sanjay Natarajan

Sanjay Natarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor with strain-inducing structure in channel
    Publication number: 20060084216
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Application
    Filed: December 1, 2005
    Publication date: April 20, 2006
    Inventors: Stephen Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Transistor with strain-inducing structure in channel
    Patent number: 7019326
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Stepped tip junction with spacer layer
    Publication number: 20050253192
    Abstract: Embodiments of the invention provides a stepped tip junction region between a source/drain region of a transistor and a gate. In some embodiments, a spacer of the transistor includes a tip junction spacer layer and a source/drain spacer layer.
    Type: Application
    Filed: May 17, 2004
    Publication date: November 17, 2005
    Inventors: Ibrahim Ban, Bernhard Sell, Sanjay Natarajan, Mark Bohr
  • Transistor with strain-inducing structure in channel
    Publication number: 20050106792
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Inventors: Stephen Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Forming polysilicon structures
    Publication number: 20040075119
    Abstract: A doped polysilicon structure may be formed without the need to etch doped polysilicon. The patterned polysilicon may be covered, an opening may be formed in the polysilicon covering, and then the polysilicon may be doped through the opening. As a result, awkward etching of doped polysilicon may be avoided in some cases.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 22, 2004
    Inventors: Sanjay Natarajan, Ibrahim Ban, Kevin Heidrich