Abstract: Techniques for coherency management based on coherent hierarchical cache line tracking are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a local cache. A hierarchical cache is coupled to the plurality of processor cores. The hierarchical cache is shared among the plurality of processor cores. Coherency between the plurality of processor cores and the hierarchical cache is managed by a compute coherency block (CCB). A cache line directory is provided for the CCB. The cache line directory includes a core list field and a cache line present field. A cache line operation is detected. The cache line operation is detected by the CCB. The cache line operation is represented by an entry in the cache line directory. The cache line operation is performed, based on corresponding values of the core list field and the line present field.

Abstract: An application programming interface (API) analysis system includes a data network and an API Carbon Footprint Analyzer (ACFA). The data network is configured to receive a call from a remote to onboard an application programming interface (API) in the data network and to obtain the API corresponding to the call. The ACFA is configured to scan the API to determine actual payload attributes and to compare the actual payload attributes to expected payload attributes of the API to determine a payload difference. The ACFA calculates an amount of data wastage based on the payload difference and causes a modification to the data network to reduce the amount of data wastage.

Abstract: A network-as-a-platform (NaaP) ecosystem includes a network exposure layer (NEL). The NEL includes a plurality of federated application programming interfaces (APIs) having at least a first federated API and a second federated API different from the first federated API. The NaaP ecosystem further includes a first network in operable communication with the NaaP ecosystem through the first federated API of the NEL, and a second network, different from the first network, in operable communication with the NaaP ecosystem through the second federated API of the NEL. The NEL enables the second network access to at least one capability of the first network.

Abstract: Mappings are used to parallelize and schedule large language models (LLMs) onto a target system architecture. Given the complexity of the LLM and the system architecture, there can be from tens of thousands to trillions of potential mappings, each offering varying levels of performance and energy efficiency. Identifying an optimal (or near-optimal) mapping is essential for maximizing the performance of LLM workloads. The present disclosure employs artificial intelligence to map a LLM to a system architecture, where the mapping can be determined from a combined representation of properties of the LLM and system architecture generated by a machine learning model.

Abstract: Mappings are used to parallelize and schedule large language models (LLMs) onto a target system architecture. Given the complexity of the LLM and the system architecture, there can be from tens of thousands to trillions of potential mappings, each offering varying levels of performance and energy efficiency. Identifying an optimal (or near-optimal) mapping is essential for maximizing the performance of LLM workloads. The present disclosure employs artificial intelligence to map a LLM to a system architecture, where the mapping can be determined from a combined representation of properties of the LLM and system architecture generated by a machine learning model.

Abstract: Techniques for cache management based on cache management using memory queues are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a common memory structure coupled to the plurality of processor cores. Coherency for the coherency domain is managed using a compute coherency block (CCB). The CCB includes a memory queue for controlling transfer of cache lines determined by the CCB. The memory queue includes an evict queue and a miss queue. Snoop requests are generated by the CCB. The snoop requests correspond to entries in the memory queue. Cache lines are transferred between the CCB and a bus interface unit. The transferring is controlled by the memory queue. The bus interface unit controls memory accesses.

Abstract: Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

Abstract: A network-as-a-platform (NaaP) ecosystem includes a network exposure layer (NEL). The NEL includes a plurality of federated application programming interfaces (APIs) having at least a first federated API and a second federated API different from the first federated API. The NaaP ecosystem further includes a first network in operable communication with the NaaP ecosystem through the first federated API of the NEL, and a second network, different from the first network, in operable communication with the NaaP ecosystem through the second federated API of the NEL. The NEL enables the second network access to at least one capability of the first network.

Abstract: There is provided a system (900) and a vehicle (1). The system (900) comprises a front crossmember (810) for the vehicle (1), and a bumper rail (840) for positioning a front bumper assembly (8, 8A) of the vehicle (1). The front crossmember (810) comprises: a first body fixing point (812) securable to a vehicle body (100) of the vehicle (1) at a first lateral side of the vehicle body (100); a second body fixing point (812) securable to the vehicle body (100) at a second lateral side of the vehicle body (100); and bumper rail fixing points (824) configured to receive the bumper rail (840). The bumper rail (840) comprises: bumper assembly positioning points (858A, 858B) for setting a position of the front bumper assembly (8, 8A) in a direction; and a ranging sensor mount (854) to support a ranging sensor (860).

Abstract: Techniques for coherency management using distributed snoop requests are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a shared memory structure coupled to the plurality of processor cores. Snoop requests are ordered in a two-dimensional matrix. The snoop requests are based on physical addresses for the shared memory structure. The two-dimensional matrix is extensible along each axis of the two-dimensional matrix. Snoop responses are mapped to a first-in first-out (FIFO) mapping queue. Each snoop response corresponds to a snoop request. Each processor core of the plurality of processor cores is coupled to at least one FIFO mapping queue. A memory access operation is completed, based on a comparison of the snoop requests and the snoop responses.

Abstract: Techniques for neural network processing using specialized data representation are disclosed. Input data for manipulation in a layer of a neural network is obtained. The input data includes image data, where the image data is represented in bfloat16 format without loss of precision. The manipulation of the input data is performed on a processor that supports single-precision operations. The input data is converted to a 16-bit reduced floating-point representation, where the reduced floating-point representation comprises an alternative single-precision data representation mode. The input data is manipulated with one or more 16-bit reduced floating-point data elements. The manipulation includes a multiply and add-accumulate operation. The manipulation further includes a unary operation, a binary operation, or a conversion operation. A result of the manipulating is forwarded to a next layer of the neural network.

Abstract: Cache management techniques are disclosed. A plurality of processor cores is accessed. Each processor core includes a shared local cache. The shared local cache supports snoop operations. A snoop queue is coupled to the plurality of processor cores. The snoop queue is shared among the plurality of processor cores. Two or more snoop operations are received for the shared local cache. The two or more snoop operations point to a common cache-line physical address within the shared local cache. The two or more snoop operations are enqueued in the snoop queue. A snoop response is generated to a first snoop operation of the two or more snoop operations. A cache eviction operation is prevented from completing, based on the snoop response being completed with a positive cache-line physical address comparison. The cache-line physical address comparison comprises a partial cache-line physical address comparison.

Abstract: Techniques for coherent processor cache control are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a shared local cache, and the plurality of processor cores implements special cache coherency operations. An evict buffer is coupled to the plurality of processor cores. The evict buffer is shared among the plurality of processor cores, and the evict buffer enables delayed writes. Evict buffer writes are monitored. The monitoring evict buffer writes identifies a special cache coherency operation. The special cache coherency operation that was identified comprises a global snoop operation. The global snoop operation is initiated from a non-local agent within a globally coherent system. An evict buffer entry is marked. The marking corresponds to the special cache coherency operation that was identified, and the marking enables management of cache evict duplication.

Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.

Abstract: A medical information system and method comprise at least one processor coupled to at least one computer storage device; a network interface enabling connectivity with one or more medical information systems and with one or more user devices; an artificial intelligence (AI) engine configured to process a request from a user device to interpret a context and a meaning from the request and to generate a response based on context and meaning of the request and data and information from the one or more medical information systems; and a user interface module configured to output the response. The AI engine can be configured to generate an interactive audiovisual response, which can include content search and generation.

Abstract: A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.

Abstract: The invention provides for optimized binuclease fusion proteins with increased pharmacokinetic properties. The optimized binuclease fusion proteins of the invention two or more nuclease domains (e.g., RNase and DNase domain) operably coupled to an Fc domain. The invention also provides methods of treating or preventing a condition associated with an abnormal immune response.

Abstract: The invention provides for optimized binuclease fusion proteins with increased pharmacokinetic properties. The optimized binuclease fusion proteins of the invention two or more nuclease domains (e.g., RNase and DNase domain) operably coupled to an Fc domain. The invention also provides methods of treating or preventing a condition associated with an abnormal immune response.

Abstract: Techniques for coherency management based on coherent hierarchical cache line tracking are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a local cache. A hierarchical cache is coupled to the plurality of processor cores. The hierarchical cache is shared among the plurality of processor cores. Coherency between the plurality of processor cores and the hierarchical cache is managed by a compute coherency block (CCB). A cache line directory is provided for the CCB. The cache line directory includes a core list field and a cache line present field. A cache line operation is detected. The cache line operation is detected by the CCB. The cache line operation is represented by an entry in the cache line directory. The cache line operation is performed, based on corresponding values of the core list field and the line present field.