Abstract: Techniques for coherent processor cache control are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a shared local cache, and the plurality of processor cores implements special cache coherency operations. An evict buffer is coupled to the plurality of processor cores. The evict buffer is shared among the plurality of processor cores, and the evict buffer enables delayed writes. Evict buffer writes are monitored. The monitoring evict buffer writes identifies a special cache coherency operation. The special cache coherency operation that was identified comprises a global snoop operation. The global snoop operation is initiated from a non-local agent within a globally coherent system. An evict buffer entry is marked. The marking corresponds to the special cache coherency operation that was identified, and the marking enables management of cache evict duplication.

Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.

Abstract: A medical information system and method comprise at least one processor coupled to at least one computer storage device; a network interface enabling connectivity with one or more medical information systems and with one or more user devices; an artificial intelligence (AI) engine configured to process a request from a user device to interpret a context and a meaning from the request and to generate a response based on context and meaning of the request and data and information from the one or more medical information systems; and a user interface module configured to output the response. The AI engine can be configured to generate an interactive audiovisual response, which can include content search and generation.

Abstract: A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.

Abstract: The invention provides for optimized binuclease fusion proteins with increased pharmacokinetic properties. The optimized binuclease fusion proteins of the invention two or more nuclease domains (e.g., RNase and DNase domain) operably coupled to an Fc domain. The invention also provides methods of treating or preventing a condition associated with an abnormal immune response.

Abstract: The invention provides for optimized binuclease fusion proteins with increased pharmacokinetic properties. The optimized binuclease fusion proteins of the invention two or more nuclease domains (e.g., RNase and DNase domain) operably coupled to an Fc domain. The invention also provides methods of treating or preventing a condition associated with an abnormal immune response.

Abstract: Techniques for coherency management based on coherent hierarchical cache line tracking are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a local cache. A hierarchical cache is coupled to the plurality of processor cores. The hierarchical cache is shared among the plurality of processor cores. Coherency between the plurality of processor cores and the hierarchical cache is managed by a compute coherency block (CCB). A cache line directory is provided for the CCB. The cache line directory includes a core list field and a cache line present field. A cache line operation is detected. The cache line operation is detected by the CCB. The cache line operation is represented by an entry in the cache line directory. The cache line operation is performed, based on corresponding values of the core list field and the line present field.

Abstract: Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group's left eight bytes and the second group's left eight bytes. A second result is based on the summation of eight values that are products of the first group's left eight bytes and the second group's right eight bytes. Results are output.

Abstract: An umbrella case configured to hold an umbrella having a rigid shaft with a handle at one end and a spike at the other end, the umbrella case comprising an umbrella holding assembly comprising a generally tubular sheath 106 having an open end and a spike-receiving portion 107 defining a spike-receiving aperture at the other end, and a fastening strap 100 having a first end coupled to an outer surface of the umbrella case, close to the open end of the sheath 106, and having a second, free end configured to be selectively moved to a fastening position in which it is connected to the umbrella case at a generally diametrically opposite location to the first end, the sheath, the spike-receiving portion and the fastening strap when in the fastening position, together, defining the effective length of the umbrella holding assembly, wherein at least one of the sheath, the spike-receiving portion and the fastening strap is selectively longitudinally extendible upon application of a force, in use, thereby to increase t

Abstract: The invention provides for optimized binuclease fusion proteins with increased pharmacokinetic properties. The optimized binuclease fusion proteins of the invention two or more nuclease domains (e.g., RNase and DNase domain) operably coupled to an Fc domain. The invention also provides methods of treating or preventing a condition associated with an abnormal immune response.

Abstract: Techniques for processor request arbitration using access request dynamic multilevel arbitration are disclosed. A plurality of processor cores is accessed. The plurality of processor cores is coupled to a memory subsystem. A plurality of access requests is generated within the processor cores coupled to the memory subsystem. The plurality of access requests is generated by the plurality of processor cores. Multiple access requests are made in a single processor cycle. Only one access request is serviced in a single processor cycle. A set of at least two criteria is associated to each access request in the plurality of access requests criteria which are dynamically assigned. The requests are organized in two vectors and a stack. The vectors are organized as linear vectors. The stack is organized as a push-pop stack. The request is granted, based on data in the two vectors and the stack.

Abstract: Techniques for cache management based on cache management using memory queues are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a common memory structure coupled to the plurality of processor cores. Coherency for the coherency domain is managed using a compute coherency block (CCB). The CCB includes a memory queue for controlling transfer of cache lines determined by the CCB. The memory queue includes an evict queue and a miss queue. Snoop requests are generated by the CCB. The snoop requests correspond to entries in the memory queue. Cache lines are transferred between the CCB and a bus interface unit. The transferring is controlled by the memory queue. The bus interface unit controls memory accesses.

Abstract: An umbrella case configured to hold an umbrella having a rigid shaft with a handle at one end and a spike at the other end, the umbrella case comprising an umbrella holding assembly comprising a generally tubular sheath 106 having an open end and a spike-receiving portion 107 defining a spike-receiving aperture at the other end, and a fastening strap 100 having a first end coupled to an outer surface of the umbrella case, close to the open end of the sheath 106, and having a second, free end configured to be selectively moved to a fastening position in which it is connected to the umbrella case at a generally diametrically opposite location to the first end, the sheath, the spike-receiving portion and the fastening strap when in the fastening position, together, defining the effective length of the umbrella holding assembly, wherein at least one of the sheath, the spike-receiving portion and the fastening strap is selectively longitudinally extendible upon application of a force, in use, thereby to increase t

Abstract: Techniques for coherency management using distributed snoop requests are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a shared memory structure coupled to the plurality of processor cores. Snoop requests are ordered in a two-dimensional matrix. The snoop requests are based on physical addresses for the shared memory structure. The two-dimensional matrix is extensible along each axis of the two-dimensional matrix. Snoop responses are mapped to a first-in first-out (FIFO) mapping queue. Each snoop response corresponds to a snoop request. Each processor core of the plurality of processor cores is coupled to at least one FIFO mapping queue. A memory access operation is completed, based on a comparison of the snoop requests and the snoop responses.

Abstract: Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group's left eight bytes and the second group's left eight bytes. A second result is based on the summation of eight values that are products of the first group's left eight bytes and the second group's right eight bytes. Results are output.

Abstract: Techniques for coherency management based on processor and network-on-chip coherency management are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores accesses a common memory through a coherent network-on-chip. The coherent network-on-chip comprises a global coherency. A local cache is coupled to a grouping of two or more processor cores. The local cache is shared among the two or more processor cores. The grouping of two or more processor cores and the shared local cache operates using local coherency. The local coherency is distinct from the global coherency. A cache maintenance operation is performed in the grouping of two or more processor cores and the shared local cache. The cache maintenance operation generates cache coherency transactions between the global coherency and the local coherency. The cache coherency transactions enable coherency among the plurality of processor cores, local caches, and the memory.

Abstract: Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

Abstract: An umbrella case configured to hold an umbrella having a rigid shaft with a handle at one end and a spike at the other end, the umbrella case comprising an umbrella holding assembly comprising a generally tubular sheath 106 having an open end and a spike-receiving portion 107 defining a spike-receiving aperture at the other end, and a fastening strap 100 having a first end coupled to an outer surface of the umbrella case, close to the open end of the sheath 106, and having a second, free end configured to be selectively moved to a fastening position in which it is connected to the umbrella case at a generally diametrically opposite location to the first end, the sheath, the spike-receiving portion and the fastening strap when in the fastening position, together, defining the effective length of the umbrella holding assembly, wherein at least one of the sheath, the spike-receiving portion and the fastening strap is selectively longitudinally extendible upon application of a force, in use, thereby to increase t

Abstract: Techniques for neural network processing using specialized data representation are disclosed. Input data for manipulation in a layer of a neural network is obtained. The input data includes image data, where the image data is represented in bfloat16 format without loss of precision. The manipulation of the input data is performed on a processor that supports single-precision operations. The input data is converted to a 16-bit reduced floating-point representation, where the reduced floating-point representation comprises an alternative single-precision data representation mode. The input data is manipulated with one or more 16-bit reduced floating-point data elements. The manipulation includes a multiply and add-accumulate operation. The manipulation further includes a unary operation, a binary operation, or a conversion operation. A result of the manipulating is forwarded to a next layer of the neural network.