Patents by Inventor Sanjay Patel

Sanjay Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210373897
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 2, 2021
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Patent number: 11190414
    Abstract: A method for providing individualized communication service includes (1) recognizing a first client being communicatively coupled to a first local communication network, (2) determining an identity of the first client, (3) transporting first data between the first client and a first operator communication network, using the first local communication network in accordance with a first service profile associated with the first client, and (4) transporting the first data using the first operator communication network in accordance with the first service profile.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 30, 2021
    Assignee: Cable Television Laboratories, ino.
    Inventors: Brian A. Scriber, Brian Stahlhammer, Darshak Thakore, Martha Lurie Lyons, Sanjay Patel, Stephen Arendt
  • Patent number: 11080062
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 3, 2021
    Assignee: MIPS Tech, LLC
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Publication number: 20210170802
    Abstract: It is provided a pneumatic tyre, the tyre having a circumferential direction, an axial direction and an equatorial plane, and the tyre comprising: a tread extending in a tyre circumferential direction, said tread comprising at least one circumferential groove running continuously in the circumferential direction, and a plurality of axial grooves or transverse grooves running at an angle to the axial direction, and a plurality of blocks defined by the circumferential groove and the axial grooves or transverse grooves, said blocks extending radially between an inner surface of the tread and a tread surface to come into contact with the ground, wherein at least some of the blocks comprise at least one wavy groove that extends from a circumferential groove inwardly into the block, and wherein the wavy groove has a depth extending radially from the tread surface to come into contact with the ground towards the inner surface that ends above the inner surface (26) of the tread.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 10, 2021
    Inventors: Mihar VED, Sanjay PATEL, Jelin FATIMA, Marko VESELINOVIC
  • Publication number: 20210034979
    Abstract: Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group's left eight bytes and the second group's left eight bytes. A second result is based on the summation of eight values that are products of the first group's left eight bytes and the second group's right eight bytes. Results are output.
    Type: Application
    Filed: August 5, 2020
    Publication date: February 4, 2021
    Inventors: James Hippisley Robinson, Sanjay Patel
  • Publication number: 20210022827
    Abstract: Taught herein is a new contact-based optical imaging technology, en-face differential optical topography (en-face DOT), which performs real-time visualization of subsurface tissue heterogeneity within a depth up to 3 mm and over a 9.5 mm diameter FOV with a modest mm-level lateral resolution. An embodiment of the probe fits in a 12 mm port and houses at its maximum 128 cop-per-coated 750 ?m fibers that form radially alternating illumination (70 fibers) and detection (58 fibers) channels. By simultaneously illuminating the 70 source channels of the laparoscopic probe that is in contact with a scattering medium and concurrently measuring the light diffusely propagated to the 58 detector channels, the presence of near-surface optical heterogeneities can be resolved in an en-face 9.5 mm field-of-view in real-time. Visualization of subsurface margin of strong attenuation contrast at a depth up to 3 mm is demonstrated at one wavelength at a frame rate of 1.3 Hz.
    Type: Application
    Filed: July 17, 2017
    Publication date: January 28, 2021
    Inventors: DAQING PIAO, SANJAY PATEL
  • Patent number: 10780266
    Abstract: Various embodiments provide methods and systems for the biphasic iontophoretic transdermal delivery of therapeutic agents. An embodiment of a method for such delivery comprises positioning at least one electrode assembly in electrical communication with a patient's skin. The assembly includes a solution comprising a therapeutic agent which passively diffuses into the skin. A dose of agent is delivered from the assembly into the skin during a first period using a first current having a characteristic e.g., polarity and magnitude, to repel the agent out of the assembly. During a second period, a second current having a characteristic to attract the agent is used to retain the agent in the assembly such that delivery of agent into skin is minimized. A dose of agent may be delivered on demand by an input from the patient. Embodiments may be used for delivery of agents which cause adverse effects from unwanted passive diffusion.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: September 22, 2020
    Assignee: InCube Labs, LLC
    Inventors: Mir Imran, Mir Hashim, Glen McLaughlin, Huma Arastu, Rekha Vaidyanathan, Joel Harris, Radhika Korupolu, Andrew Mangogna, Chang Ong, Sanjay Patel, Lu Wang, Timothy Williams
  • Publication number: 20200296014
    Abstract: A method for providing individualized communication service includes (1) recognizing a first client being communicatively coupled to a first local communication network, (2) determining an identity of the first client, (3) transporting first data between the first client and a first operator communication network, using the first local communication network in accordance with a first service profile associated with the first client, and (4) transporting the first data using the first operator communication network in accordance with the first service profile.
    Type: Application
    Filed: November 20, 2019
    Publication date: September 17, 2020
    Inventors: Brian A. Scriber, Brian Stahlhammer, Darshak Thakore, Martha Lurie Lyons, Sanjay Patel, Stephen Arendt
  • Publication number: 20200264783
    Abstract: Aspects relate to Input/Output (TO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Sanjay Patel, Ranjit J. ROZARIO
  • Publication number: 20200225955
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 16, 2020
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Publication number: 20200202195
    Abstract: Techniques for neural network processing using mixed-precision data representation are disclosed. Access to a processor that supports single-precision operations is obtained, where the processor is used for neural network calculations. A first input data element and a second input data element are presented for manipulation on the processor, where the manipulation supports the neural network calculations. The first input data element is manipulated with the second input data element using the processor, where the first input data element comprises a 16-bit reduced floating point representation. A result of the manipulation is output, where the result comprises a single-precision data representation element. The result is forwarded to a next layer of the neural network, based on the outputting.
    Type: Application
    Filed: January 31, 2020
    Publication date: June 25, 2020
    Inventor: Sanjay Patel
  • Publication number: 20200184309
    Abstract: Techniques for neural network processing using specialized data representation are disclosed. Input data for manipulation in a layer of a neural network is obtained. The input data includes image data, where the image data is represented in bfloat16 format without loss of precision. The manipulation of the input data is performed on a processor that supports single-precision operations. The input data is converted to a 16-bit reduced floating-point representation, where the reduced floating-point representation comprises an alternative single-precision data representation mode. The input data is manipulated with one or more 16-bit reduced floating-point data elements. The manipulation includes a multiply and add-accumulate operation. The manipulation further includes a unary operation, a binary operation, or a conversion operation. A result of the manipulating is forwarded to a next layer of the neural network.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Inventor: Sanjay Patel
  • Patent number: 10664280
    Abstract: A fetch ahead branch target buffer is used by a branch predictor to determine a target address for a branch instruction based on a fetch pointer for a previous fetch bundle, i.e. a fetch bundle which is fetched prior to a fetch bundle which includes the branch instruction. An entry in the fetch ahead branch target buffer corresponds to one branch instruction and comprises a data portion identifying the target address of that branch instruction. In various examples, an entry also comprises a tag portion which stores data identifying the fetch pointer by which the entry is indexed. Branch prediction is performed by matching an index generated using a received fetch pointer to the tag portions to identify a matching entry and then determining the target address for the branch instruction from the data portion of the matching entry.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 26, 2020
    Assignee: MIPS Tech, LLC
    Inventors: Parthiv Pota, Sanjay Patel, Sudhakar Ranganathan
  • Patent number: 10649773
    Abstract: A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: May 12, 2020
    Assignee: MIPS Tech, LLC
    Inventors: Ranjit J. Rozario, Andrew F. Glew, Sanjay Patel, James Robinson, Sudhakar Ranganathan
  • Patent number: 10642501
    Abstract: Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: May 5, 2020
    Assignee: MIPS Tech, LLC
    Inventors: Sanjay Patel, Ranjit J Rozario
  • Patent number: 10635159
    Abstract: Adaptive voltage modulation circuits for adjusting supply voltage to reduce supply voltage droops and minimize power consumption are provided. In one aspect, an adaptive voltage modulation circuit detects a supply voltage droop by detecting when a supply voltage falls below a droop threshold voltage, and adjusts a clock signal provided to a load circuit in response to a supply voltage droop. The adaptive voltage modulation circuit keeps a count of the number of clock signal cycles during which the supply voltage is below the droop threshold voltage. The adaptive voltage modulation circuit increases the supply voltage in response to the count exceeding an upper threshold value, and decreases the supply voltage in response to the count being less than a lower threshold value at an end of a defined period. The adaptive voltage modulation circuit can reduce the time a load circuit operates with reduced frequency while minimizing power consumption.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: April 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yeshwant Nagaraj Kolla, Jeffrey Todd Bridges, Sanjay Patel, Shraddha Sridhar, Burt Lee Price, Gabriel Martel Tarr
  • Publication number: 20200058045
    Abstract: Systems and methods for gamification-based engagement are disclosed. In one embodiment, in an information processing apparatus comprising at least one computer processor, a method for gamification-based engagement, may include: (1) receiving, from a plurality of data sources, customer activity data comprising customer behavioral data and customer transactional data for a plurality of customers; (2) generating a dynamic customer profile for each of the customers based on the customer activity data and the customer transactional data; (3) retrieving challenge data for a challenge comprising an identification of a plurality of tasks to be completed, an order in which the tasks are to be completed, and an incentive for completing the tasks; (4) dynamically matching one of the customers to the challenge; (5) issuing the challenge to the customer; (6) tracking the customer's response to the challenge; and (7) updating the customer's dynamic customer profile based on the customer's response.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 20, 2020
    Inventors: Shuchi PATEL, Kristie ISOM, John Robert CLEM, Edgar A. VERCHOT, III, Gerardo GEAN, Konstandina DEMERELL, Sanjay PATEL, Raghuram VUDATHU, Julia ELYASHEVA, David Christopher CAREY
  • Publication number: 20190324631
    Abstract: This document presents a system and method for assessing the state of an electric switch cover that is configured to control one, two or four separate control circuits upon the user depressing an electric switch cover portion associated with the switch area for each control circuit. Each time a user depresses the electric switch cover portion, a pressure signal is sent to a processor installed within the switch identifying the electric circuit associated with that portion of the electric switch cover. The processor determines the configuration of devices, experiences, and/or triggers associated with the selected electric circuit and sends an activation signal through the electric circuit. A user thus may customize the control of multiple configurable devices and experiences in any space in a user's home.
    Type: Application
    Filed: April 20, 2018
    Publication date: October 24, 2019
    Inventor: Sanjay Patel
  • Publication number: 20190241878
    Abstract: The invention provides for optimized binuclease fusion proteins with increased pharmacokinetic properties. The optimized binuclease fusion proteins of the invention two or more nuclease domains (e.g., RNase and DNase domain) operably coupled to an Fc domain. The invention also provides methods of treating or preventing a condition associated with an abnormal immune response.
    Type: Application
    Filed: June 30, 2017
    Publication date: August 8, 2019
    Inventors: James Arthur POSADA, Sanjay PATEL, Weihong YU, Chris GABEL
  • Patent number: 10365727
    Abstract: A method of character recognition for a personal computing device comprising a user interface capable of receiving inputs that are to be recognized through data input means which are receptive to keyed, tapped or a stylus input, said device being adapted to facilitate a reduction in the number of physical keying actions, tapping actions or gestures required to create a data string to less than the number of characters within said data string: storing a set of data strings each with a priority indicator associated therewith, wherein the indicator is a measure of a plurality of derivatives associated with the data string; recognizing an event; looking up the most likely subsequent data string to follow the event from the set of data strings based on one or more of the plurality of derivatives; ordering the data strings for display based on the priority indicator of that data string.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: July 30, 2019
    Assignee: Keypoint Technologies (UK) Limited
    Inventors: Sunil Motaparti, Sanjay Patel