Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.

Abstract: A method of forming bare silicon substrates is described. A bare silicon substrate is measured, wherein measuring is performed by a non-contact capacitance measurement device to obtain a signal at a point on the substrate. The signal or a thickness indicated by the signal is communicated to a controller. An adjusted polishing parameter according to the signal or thickness indicated by the signal is determined. After determining an adjusted polishing parameter, the bare silicon substrate is polished on a polisher using the adjusted polishing parameter.

Abstract: Methods and apparatus, including computer program products, for targeted location-based messaging. A method includes, in a server residing in a network of interconnected computers, the server including a processor and a memory, maintaining a repository of content, receiving geolocation information from a mobile device, determining appropriate content to be sent to the mobile device according to the received geolocation location information, and sending the appropriate content to the mobile device for projection on to a projection surface.

Abstract: Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.

Abstract: An embodiment may include circuitry to determine, at least in part, based at least in part upon history information, whether one or more reference patterns are present in a data stream in a packet flow. The data stream may span at least one packet boundary in the packet flow. The history information may include a beginning portion of a packet in the data stream, an ending portion of the packet, and another portion of the data stream. The circuitry may overwrite the another portion of the history information with a respective portion of the data stream to be examined by the circuitry depending, at least in part, upon whether the circuitry determines, at least in part, whether the one or more reference patterns are present in the data stream. The respective portion may be relatively closer than the another portion is to a beginning of the data stream.

Abstract: A system, apparatus, method and article to reduce power consumption are described. The method may include receiving a power management request for a reduced power consumption state from each of a plurality of processors. A power management request for the reduced power consumption state may be sent to a controller to cache data. Each of the plurality of processors may be instructed to enter the reduced power consumption state. An interrupt may be received to return to an active power consumption state. A power management request may be sent to the controller to flush cached data into a memory. Each of the plurality of processors may be instructed to enter the active power consumption state. Other embodiments are described and claimed.

Abstract: In general, in one aspect, the disclosure describes a processor that includes multiple multi-threaded programmable units integrated on a single die. The die also includes circuitry communicatively coupled to the programmable units that reorders and grants lock requests received from the threads based on an order in which the threads requested insertion into a sequence of lock grants.

Abstract: Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.

Abstract: Scheduling of packets is performed by a scheduler based on departure times. If wrap up of departure times is possible, departure times are transposed based on a zone associated with the last departure time. By using the zone to transpose in order to sort departure times, cycles of independent checks on each of the departure times are avoided.

Abstract: A method of forming bare silicon substrates is described. A bare silicon substrate is measured, wherein measuring is performed by a non-contact capacitance measurement device to obtain a signal at a point on the substrate. The signal or a thickness indicated by the signal is communicated to a controller. An adjusted polishing parameter according to the signal or thickness indicated by the signal is determined. After determining an adjusted polishing parameter, the bare silicon substrate is polished on a polisher using the adjusted polishing parameter.

Abstract: Method and apparatus to manage flow control for a network device are described.

Abstract: A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element.

Abstract: A method and apparatus for scheduling packets using a pre-sort deficit round-robin method. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. A packet is transmitted by dequeuing the packet from the pre-sorted scheduling array.

Abstract: Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devices. The method and apparatus employ queue descriptors to manage transfer of data from corresponding queues in memory into a switch fabric. In one embodiment, each queue descriptor includes an enqueue pointer identifying a tail cell of a segment of data scheduled to be transferred from the queue, a schedule pointer identifying a head cell of the segment of data, and a commit pointer identifying a most recent cell in the segment of data to be successfully transmitted into the switch fabric. In another embodiment, the queue descriptor further includes a scheduler sequence number; and a committed sequence number that are employed in connection with transfers of data from queues containing multiple segments. The various pointers and sequence numbers are employed to facilitate efficient check-point and roll-back operations relating to unsuccessful transmissions into the switch fabric.

Abstract: In general, in one aspect, the disclosure describes a method that includes at a first packet processing thread executing at a first core, performing a memory read to data shared between packet processing threads including the first thread. The method also includes at the first packet processing thread, determining whether the data returned by the memory read has been changed by a packet processing thread operating on another core before performing an exclusive operation on the shared data by the first packet processing thread.

Abstract: Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.

Abstract: Systems and methods employing a flexible mesh structure for hierarchical scheduling are disclosed. The method generally includes reading a packet grouping configured in a two dimensional mesh structure of N columns, each containing M packets, selecting and promoting a column best packet from each column to a final row containing N packets, reading, selecting and promoting a final best packet from the final row to a next level in the hierarchy. Each time a final best packet is selected and promoted, the mesh structure can be refreshed by replacing the packet corresponding to the final best packet, and reading, selecting and promoting a column best packet from the column containing the replacement packet to the final row. As only the column containing the replacement packet and the final row are read and compared for each refresh, the mesh structure results in reduced read and compare cycles for schedule determination.

Abstract: A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.

Abstract: A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.

Abstract: A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to read-modify-write commands.