Abstract: Method and apparatus to manage flow control for a network device are described.

Abstract: Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

Abstract: Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store.

Abstract: A system having queue control structures includes a conflict avoidance mechanism to prevent memory bank conflicts for queue descriptor access. In one embodiment, a queue descriptor bank table contains information including in which memory bank each queue descriptor is stored.

Abstract: Provided are a method, system, network processor, network device, and article of manufacture for enqueueing entries in a packet queue referencing packets. When adding a packet to a first memory area, an entry is written to a packet queue in a second memory area referencing the added packet. A pointer is read referencing one end of the packet queue from a queue descriptor in the second memory area into a third memory area in one read operation.

Abstract: A system that queues data packets includes efficient memory access of queue control data structures.

Abstract: A method and apparatus for scheduling packets using one or more pre-sort scheduling arrays. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. Packets may be scheduled according to a non-work conserving technique, or packets may be scheduled according to a work conserving technique. A packet is transmitted by dequeuing the packet from a pre-sorted scheduling array.

Abstract: A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.

Abstract: A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.

Abstract: A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.

Abstract: A method and apparatus for scheduling packets using a pre-sort deficit round-robin method. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. A packet is transmitted by dequeuing the packet from the pre-sorted scheduling array.

Abstract: In general, in one aspect, the disclosure describes a method of tracking a network statistic stored within a collection of bits. The method includes storing the collection of bits storing the network statistic as at least a first portion and a second portion. The first portion includes a set of least-significant bits and the second portion includes a set of more significant bits. The method also includes incrementing the first portion based on a packet and=determining if the incrementing of the first portion caused a designated bit of the first portion to be set. If it is determined that the incrementing of the first portion caused the designated bit to be set, the method increments the value stored by the second portion and resets the designated bit within the first portion.

Abstract: The present invention relates to novel primers useful for identifying and screening non-sense mutation with codon TGG coding for amino acid tryptophan substituted with TAG a non-sense codon at nucleotide No. 825 in exon 2 of synaptogyrin 1 gene of chromosome 22q11-13, thereby detecting pre-disposition to schizophrenia in a subset of patients and a method thereof.

Abstract: Two sequential treatments within a chemical vapor deposition chamber, or within sequential chambers without a vacuum break, are performed on a copper layer to clean and passivate the copper surface prior to deposition of a copper diffusion barrier layer or a dielectric layer. The first treatment includes an ammonia, a hydrogen, or a hydrocarbon plasma cleaning of the copper surface followed by a short initiation of an organosilane precursor or a thin silicon nitride layer. A copper diffusion barrier layer may then be formed over the pretreated copper surface using an organosilane plasma, with or without a carbon dioxide or a carbon monoxide, or a silane with a nitrogen gas and an ammonia gas. Copper diffusion is retarded and film adhesion is improved for a dielectric layer or a copper diffusion barrier layer on the copper surface.

Abstract: A PCI and PCI-X bus-bridging method and apparatus is described. Posted memory write requests and requests not allowed to execute before a prior posted memory write are written to one queue. Requests that are allowed to pass a posted memory write are written to a separate second queue. Requests at the head of these queues receiving a RETRY response or failing to execute completely are removed from the queue and stored in a Retry List. Requests execute depending on which one of them wins control of the destination bus. The posted memory writes queue and any request not allowed to pass a posted memory write are blocked from executing if there is a location in the Retry List occupied by a posted memory write.

Abstract: The present invention relates to novel primers useful for identifying and screening non-sense mutation with codon TGG coding for amino acid tryptophan substituted with TAG a non-sense codon at nucleotide No. 825 in exon 2 of synaptogyrin 1 gene of chromosome 22q11-13, thereby detecting pre-disposition to schizophrenia in a subset of patients and a method thereof.

Abstract: An amorphous material containing silicon, carbon, hydrogen and nitrogen, provides a barrier/etch stop layer for use with low dielectric constant insulating layers and copper interconnects. The amorphous material is prepared by plasma assisted chemical vapor deposition (CVD) of alklysilanes together with nitrogen and ammonia. Material that at the same time has a dielectric constant less than 4.5, an electrical breakdown field about 5 MV/cm, and a leakage current less than or on the order of 1 nA/cm2 at a field strength of 1 MV/cm has been obtained. The amorphous material meets the requirements for use as a barrier/etch stop layer in a standard damascene fabrication process.

Abstract: This invention relates to a method of depositing silicon oxide films on the surface of semiconductor substrates, and more particularly to depositing such films by chemical vapor deposition using alkylsiloxane oligomers precursors with ozone.

Abstract: A PCI and PCI-X bus-bridging method and apparatus is described. Posted memory write requests and requests not allowed to execute before a prior posted memory write are written to one queue. Requests that are allowed to pass a posted memory write are written to a separate second queue. Requests at the head of these queues receiving a RETRY response or failing to execute completely are removed from the queue and stored in a Retry List. Requests execute depending on which one of them wins control of the destination bus. The posted memory writes queue and any request not allowed to pass a posted memory write are blocked from executing if there is a location in the Retry List occupied by a posted memory write.

Abstract: An amorphous material containing silicon, carbon, hydrogen and nitrogen, provides a barrier/etch stop layer for use with low dielectric constant insulating layers and copper interconnects. The amorphous material is prepared by plasma assisted chemical vapor deposition (CVD) of alklysilanes together with nitrogen and ammonia. Material that at the same time has a dielectric constant less than 4.5, an electrical breakdown field about 5 MV/cm, and a leakage current less than or on the order of 1 nA/cm2 at a field strength of 1 Mv/cm has been obtained. The amorphous material meets the requirements for use as a barrier/etch stop layer in a standard damascene fabrication process.