Abstract: The present disclosure provides a memory device, which includes a memory array, a read-clock generation circuit, and a local input/output circuit. The read-clock generation circuit receives a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal. The local input/output circuit includes multiple pairs of column-address pass gates, and a pair of read pass gates. The plurality of pairs of column-address pass gates are configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal. The pair of read pass gates connects a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state. The first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

Abstract: Devices, circuits, and methods are provided. A circuit comprises a tracking word line circuit that is configured to receive an internal clock signal, a turbo signal, and a read enable signal, and to generate a first tracking reading signal and a first tracking writing signal in response to the internal clock signal the turbo signal, and the write enable signal. The circuit also comprises a tracking bit line circuit configured to receive the first tracking reading signal and the first tracking writing signal, wherein the tracking bit line circuit is configured to generate a tracking bit line signal in response to the first tracking reading signal and the first tracking writing signal, wherein the tracking word line circuit is configured to generate a reset signal in response to the tracking bit line signal and transmit the reset signal to the clock generator.

Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal.

Abstract: A system includes a processing device and a memory device that includes instructions executable by the processing device for causing the processing device to perform operations. The operations include receiving a first configuration update of a first interaction event. The operations further include automatically switching a test channel connection with an interaction processing environment, using the first configuration update of the first interaction event, to generate a first switched channel connection with the interaction processing environment. Additionally, the operations include, in response to establishing the first switched channel connection, facilitating a first validation operation of the first configuration update using the first switched channel connection with the interaction processing environment. Further, the operations include, in response to validating the first configuration update, implementing the first configuration update in an interaction production environment.

Abstract: Systems and methods for using a differentiable multi-agent Actor-Critic (DiMAC) for multi-step radiology report summarization. The tasks of extracting salient sentences and phrases are divided across two collaborating agents that are trained end-to-end using reinforcement learning (RL).

Abstract: A device includes a Coordinate Rotation Digital Computer (CORDIC), a memory, a first Direct Memory Access (DMA) engine, and a second DMA engine. The memory stores an array of calculation data sets and an array of result data sets corresponding to the calculation data sets. The first DMA engine copies each data set of the array of calculation data sets from the memory to the CORDIC. The second DMA engine copies each result data set of the array of result data sets from the CORDIC to the memory and generates a trigger in response to copying a final result data set of the array of result data sets to the memory.

Abstract: Systems and methods for generating synthetic medical data are provided. One of 1) an input medical image, 2) input medical text, or 3) an input medical image/text pair is received. Features are extracted from the received one of 1) the input medical image, 2) the input medical text, or 3) the input medical image/text pair. One of A) synthetic medical text, B) a synthetic medical image, or C) a synthetic medical image/text pair is generated for the received one of 1) the input medical image, 2) the input medical text, or 3) the input medical image/text pair respectively based on the extracted features and using a trained machine learning based model. The generated one of A) the synthetic medical text, B) the synthetic medical image, or C) the synthetic medical image/text pair is output.

Abstract: Example systems, devices, and techniques are described for inferring a potential bad cable issue associated with a cable. An example system includes processing circuitry configured to determine a class of a cable associated with one of a plurality of network interfaces. The processing circuitry is configured to select, based on the class of the cable, a first machine learning model of a plurality of machine learning models. The processing circuitry is configured to determine, based on the class of the cable and the one of the plurality of network interfaces, a first feature set of the performance data. The processing circuitry is configured to execute the first machine learning model to infer, based on the first feature set, a potential bad cable issue associated with the cable and output an indication of the potential bad cable issue associated with the cable.

Abstract: The invented method is to realize a silicon chip carrier using wet bulk micromachining of silicon. In the silicon chip carrier, three (or more) supports are realized solely based on the wet etching of the silicon. The fabricated supports are triangular in shape and provide a minimum contact area between the sensing element and carrier. The invention provides a simple, cost-effective fabrication technology, which uses anisotropic wet etchant for silicon bulk-micromachining. A fabricated silicon wafer can be diced as per the requirement of single/multiple channel IR detectors. These chip carriers will cut down the IR detector cost with attractive lower thermal conductance in the field of gas sensors, spectrometry, thermal imaging, and fire detection.

Abstract: Disclosed herein are related to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell to store data. In one aspect, the memory device includes an output driver configured to: generate an output signal indicating the stored data, in response to a sleep tracking signal indicating that the memory cell is in the operational state, and generate the output signal having a predetermined voltage irrespective of the stored data, in response to the sleep tracking signal indicating that the memory cell is in the sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal causing the memory cell to operate in the sleep state or the operational state.

Abstract: A system provides document storage and sharing on behalf of nodes of a blockchain system. The system includes one or more databases and one or more servers. The one or more servers receive file content of a document from a first node of the blockchain system and stores the file content in the one or more databases. A file hash of the document is generated by applying a hash function to the file content. The file hash is sent to the first node, such as for sharing with one or more other authorized nodes. The one or more servers receives a request for the document from a second node of the blockchain system, the request including the file hash. In response, the one or more servers send the file content of the document to the second node.

Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.

Abstract: This invention relates to an apparatus (100) and method (400) for optimizing a commissioning process by using patterns (A, O) identified in a physical space where a lighting system is to be deployed, to thereby reduce complexity and time effort for commissioning lighting components and controls.

Abstract: A device includes a Coordinate Rotation Digital Computer (CORDIC), a memory, a first Direct Memory Access (DMA) engine, and a second DMA engine. The memory stores an array of calculation data sets and an array of result data sets corresponding to the calculation data sets. The first DMA engine copies each data set of the array of calculation data sets from the memory to the CORDIC. The second DMA engine copies each result data set of the array of result data sets from the CORDIC to the memory and generates a trigger in response to copying a final result data set of the array of result data sets to the memory.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that collect media metrics on computing devices. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to determine a permission level of a meter and, in response to the determination, request a permission to access media data of an application programming interface (API), in response to determining a media session notification is available as indicated by the API, package media session data associated with the media session notification, the media session data extracted from metadata of the media session notification, obtain foreground information; and generate a package of metrics, the package of metrics including the packaged media session data and the foreground information.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: Artificial reality (XR) experiences today typically only provide users representations of their upper body (e.g., as avatars). Although legs do not have a high range of movement or expression in XR, they are required to bring a sense of believability to digital humans represented in XR. However, tracking legs can be difficult because they are frequently not visible to XR device cameras. Aspects of the present disclosure provide a full body synthesis system that can generate plausible full body poses of users by leveraging generative machine learning, in real time, on an XR device. The full body synthesis system can be flexible to multiple numbers and types of inputs (e.g., positions/rotations/accelerations of joints, computer vision models, etc.), and can generalize users of any height, body scale, and body shape.

Abstract: A method, computer program product, and computer system for downloading, by a first computing device, code associated with processing requests directed toward a datastore, wherein the code is a new version of code to replace a prior version of code associated with processing requests directed toward the datastore. The first computing device may receive a first request directed toward the datastore, wherein the first request may be received while downloading the new version of code. The first computing device may process the first request directed toward the datastore using the prior version of code while downloading the new version of code. The first computing device may switch from the prior version of code to the new version of code.