Patents by Inventor Sanjeev Kumar Jain

Sanjeev Kumar Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11568925
    Abstract: A memory device is disclosed. The memory device includes a memory array including a first memory cell arranged in a first row and a first column and a second memory cell arranged in the first row and a second column next to the first column. The first memory cell is configured to perform a write operation in response to a first write signal transmitted through a first write word line. The second memory cell is configured to perform the write operation in response to a second write signal transmitted through a second write word line. The second write word line is separated from and next to the first write word line. The first write signal and the second write signal have different logic values.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11532335
    Abstract: A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sanjeev Kumar Jain
  • Publication number: 20220336009
    Abstract: Circuits and methods are described herein for controlling a bit line precharge circuit. For example, a control circuit includes a first latch circuit and a second latch circuit. The first latch circuit is configured to receive a first light sleep signal. The first latch circuit generates a second light sleep signal according to a clock signal. The second latch circuit is configured to receive the second light sleep signal. The second latch circuit generates a third light sleep signal according to a sense amplifier enable signal. The second latch circuit provides the third light sleep signal to a bit line reading switch, so the bit line reading switch is cutoff after a sense amplifier is enabled.
    Type: Application
    Filed: September 8, 2021
    Publication date: October 20, 2022
    Inventor: Sanjeev Kumar Jain
  • Publication number: 20220326875
    Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Inventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
  • Publication number: 20220319557
    Abstract: Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.
    Type: Application
    Filed: December 14, 2021
    Publication date: October 6, 2022
    Inventor: Sanjeev Kumar Jain
  • Publication number: 20220319564
    Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 6, 2022
    Inventor: Sanjeev Kumar Jain
  • Publication number: 20220262423
    Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.
    Type: Application
    Filed: May 6, 2022
    Publication date: August 18, 2022
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11403033
    Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
  • Publication number: 20220238144
    Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Sanjeev Kumar Jain, Sahil Preet Singh, Atul Katoch
  • Patent number: 11386942
    Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, ltd.
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11328762
    Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sanjeev Kumar Jain
  • Publication number: 20220139451
    Abstract: A memory device is disclosed. The memory device includes a memory array including a first memory cell arranged in a first row and a first column and a second memory cell arranged in the first row and a second column next to the first column. The first memory cell is configured to perform a write operation in response to a first write signal transmitted through a first write word line. The second memory cell is configured to perform the write operation in response to a second write signal transmitted through a second write word line. The second write word line is separated from and next to the first write word line. The first write signal and the second write signal have different logic values.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Sanjeev Kumar JAIN
  • Publication number: 20220130455
    Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.
    Type: Application
    Filed: May 3, 2021
    Publication date: April 28, 2022
    Inventors: Sanjeev Kumar Jain, Ruchin Jain, Arun Achyuthan, Atul Katoch
  • Patent number: 11309000
    Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sanjeev Kumar Jain, Sahil Preet Singh, Atul Katoch
  • Publication number: 20220093154
    Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Inventor: Sanjeev Kumar Jain
  • Publication number: 20220068327
    Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.
    Type: Application
    Filed: January 4, 2021
    Publication date: March 3, 2022
    Inventors: Sanjeev Kumar Jain, Sahil Preet Singh, Atul Katoch
  • Publication number: 20220068330
    Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal.
    Type: Application
    Filed: February 19, 2021
    Publication date: March 3, 2022
    Inventor: Sanjeev Kumar Jain
  • Publication number: 20220068374
    Abstract: Systems and methods are provided for a memory device. A memory device includes a memory array, a column selection circuit coupled to the memory array, where the column selection circuit is configured to generate a column selection signal, and a sense amplifier configured to receive data signals from the memory array. An enable signal generating circuit is configured to generate a first enable signal and a second enable signal. The column selection circuit generates the column selection signal based on the first enable signal, and the sense amplifier is configured to receive a data signal from the memory array in response to the second enable signal.
    Type: Application
    Filed: January 5, 2021
    Publication date: March 3, 2022
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11176972
    Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sanjeev Kumar Jain, Jaspal Singh Shah
  • Patent number: 11170830
    Abstract: Systems and method are provided for a word line driver. A first supply branch is configured to provide a source voltage level for a word line. A second supply branch is configured to provide a boosted voltage for the word line. The word line driver is configured to apply the source voltage level to the word line based on a first selection signal, and the word line driver is configured to apply the boosted voltage to the word line based on a second selection signal, the second selection signal being delayed relative to the first selection signal.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Sanjeev Kumar Jain