Abstract: Devices, circuits, and methods are provided. A circuit comprises a tracking word line circuit that is configured to receive an internal clock signal, a turbo signal, and a read enable signal, and to generate a first tracking reading signal and a first tracking writing signal in response to the internal clock signal the turbo signal, and the write enable signal. The circuit also comprises a tracking bit line circuit configured to receive the first tracking reading signal and the first tracking writing signal, wherein the tracking bit line circuit is configured to generate a tracking bit line signal in response to the first tracking reading signal and the first tracking writing signal, wherein the tracking word line circuit is configured to generate a reset signal in response to the tracking bit line signal and transmit the reset signal to the clock generator.

Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal.

Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.

Abstract: A system includes an exhaust diffuser system having an axial-radial diffuser and a transition duct. The axial-radial diffuser includes an inlet, an outlet, an axial diffuser portion between the inlet and the outlet, and a radial diffuser portion between the axial diffuser portion and the outlet, wherein the inlet is configured to couple to a gas turbine system. The transition duct is coupled to the axial-radial diffuser, wherein the outlet is disposed inside of an intake portion of the transition duct, and the transition duct includes a discharge portion configured to couple to a heat recovery steam generator (HRSG).

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.

Abstract: Circuits and methods are described herein for controlling a bit line precharge circuit. For example, a control circuit includes a first latch circuit and a second latch circuit. The first latch circuit is configured to receive a first light sleep signal. The first latch circuit generates a second light sleep signal according to a clock signal. The second latch circuit is configured to receive the second light sleep signal. The second latch circuit generates a third light sleep signal according to a sense amplifier enable signal. The second latch circuit provides the third light sleep signal to a bit line reading switch, so the bit line reading switch is cutoff after a sense amplifier is enabled.

Abstract: A memory cell is configured to store data and operate in an operational state or a sleep state. A first set of transistors is configured to transfer data from the data sensing node of the memory cell to a data latch node, in response to the memory cell being in the operational state. A second set of transistors is configured to latch the data at the data latch node, in response to the memory cell being in the operational state. A third set of transistors is configured to latch the data at the data latch node, in response to the memory cell being in the sleep state. The first set of transistors is further configured to transfer the data from the data latch node to the data sensing node of the memory cell, in response to the memory cell being transitioned from the sleep state to the operational state.

Abstract: Circuits and methods are described herein for controlling a bit line precharge circuit. For example, a control circuit includes a first latch circuit and a second latch circuit. The first latch circuit is configured to receive a first light sleep signal. The first latch circuit generates a second light sleep signal according to a clock signal. The second latch circuit is configured to receive the second light sleep signal. The second latch circuit generates a third light sleep signal according to a sense amplifier enable signal. The second latch circuit provides the third light sleep signal to a bit line reading switch, so the bit line reading switch is cutoff after a sense amplifier is enabled.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a first memory cell, a first buffer, first logic circuitry, and first switching circuitry. The first memory cell may be configured to pre-charge in response to receiving a primary sleep signal. The first buffer may be configured to receive the primary sleep signal, generate a delayed primary sleep signal, and provide the delayed primary sleep signal to a second memory cell. The first logic circuitry may be configured to generate a first bit line pre-charge signal for the first memory cell of the plurality of memory cells in response to a looped sleep signal, wherein the looped sleep signal is generated based on the delayed primary sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal.

Abstract: Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.

Abstract: Systems and methods are provided a memory circuit that provides multiple clock signals to a local clock driver. One of the clock signals may be faster than the other and, as a result, at least one transistor of the local clock driver may be turned on early to improve the delay of the rising edge, the falling edge, or both edges of the slower clock signal. The local clock driver may include a first transistor electrically connected to the NAND gate and a second transistor electrically connected to the NOR gate. As a result of the additional, faster clock signal, a reduction of the clock to word line time in the memory circuit can be achieved.

Abstract: A system includes an exhaust diffuser system having an axial-radial diffuser and a transition duct. The axial-radial diffuser includes an inlet, an outlet, an axial diffuser portion between the inlet and the outlet, and a radial diffuser portion between the axial diffuser portion and the outlet, wherein the inlet is configured to couple to a gas turbine system. The transition duct is coupled to the axial-radial diffuser, wherein the outlet is disposed inside of an intake portion of the transition duct, and the transition duct includes a discharge portion configured to couple to a heat recovery steam generator (HRSG).

Abstract: Devices, circuits, and methods are provided. A circuit comprises a tracking word line circuit that is configured to receive an internal clock signal, a turbo signal, and a read enable signal, and to generate a first tracking reading signal and a first tracking writing signal in response to the internal clock signal the turbo signal, and the write enable signal. The circuit also comprises a tracking bit line circuit configured to receive the first tracking reading signal and the first tracking writing signal, wherein the tracking bit line circuit is configured to generate a tracking bit line signal in response to the first tracking reading signal and the first tracking writing signal, wherein the tracking word line circuit is configured to generate a reset signal in response to the tracking bit line signal and transmit the reset signal to the clock generator.

Abstract: The present disclosure provides a memory device, which includes a memory array, a read-clock generation circuit, and a local input/output circuit. The read-clock generation circuit receives a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal. The local input/output circuit includes multiple pairs of column-address pass gates, and a pair of read pass gates. The plurality of pairs of column-address pass gates are configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal. The pair of read pass gates connects a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state. The first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.

Abstract: Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: A memory circuit includes a global control circuit, a first local control circuit and a first set of word line post-decoder circuits. The global control circuit is configured to generate a first and second set of global pre-decoder signals and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals. The first set of word line post-decoder circuits is configured to generate a first set of word line signals.