Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

Abstract: Systems and method are provided for a word line driver. A first supply branch is configured to provide a source voltage level for a word line. A second supply branch is configured to provide a boosted voltage for the word line. The word line driver is configured to apply the source voltage level to the word line based on a first selection signal, and the word line driver is configured to apply the boosted voltage to the word line based on a second selection signal, the second selection signal being delayed relative to the first selection signal.

Abstract: Systems and method are provided for a memory circuit. A predecoder circuit is configured to receive a first address signal, a first clock signal, and a second clock signal. The predecoder circuit is configured to generate a selection signal based on the first clock signal and the first address signal. And the predecoder circuit is further configured to maintain the selection signal based on the second clock signal and the first address signal.

Abstract: Systems and method are provided for a word line driver. A first supply branch is configured to provide a source voltage level for a word line. A second supply branch is configured to provide a boosted voltage for the word line. The word line driver is configured to apply the source voltage level to the word line based on a first selection signal, and the word line driver is configured to apply the boosted voltage to the word line based on a second selection signal, the second selection signal being delayed relative to the first selection signal.

Abstract: A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

Abstract: A voltage level shifter for an SRAM device includes a level shifter input and provides a second voltage level. A voltage input terminal receives a first signal at a first voltage level and an inverter having an input and an output with the voltage input terminal is connected to the inverter input. A first voltage selector selectively applies an intermediate voltage to the gate of a PMOS transistor in a first complementary pair when the voltage of a complementary level shift output voltage rises to a logical 1 and a second voltage selector applies the intermediate voltage to the gate of a PMOS transistor in a second complementary pair when the voltage of the level shift output voltage node rises to a logical 1. The PMOS transistor current is thereby reduced resulting in lower energy dissipation and supporting a larger voltage separation between the first and second voltage levels.

Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.

Abstract: A voltage level shifter for an SRAM device includes a level shifter input and provides a second voltage level. A voltage input terminal receives a first signal at a first voltage level and an inverter having an input and an output with the voltage input terminal is connected to the inverter input. A first voltage selector selectively applies an intermediate voltage to the gate of a PMOS transistor in a first complementary pair when the voltage of a complementary level shift output voltage rises to a logical 1 and a second voltage selector applies the intermediate voltage to the gate of a PMOS transistor in a second complementary pair when the voltage of the level shift output voltage node rises to a logical 1. The PMOS transistor current is thereby reduced resulting in lower energy dissipation and supporting a larger voltage separation between the first and second voltage levels.

Abstract: An SRAM device has a voltage input terminal configured to receive a first signal at a first voltage level. A level shifter is connected to the voltage input terminal to receive the first signal, and the level shifter is configured to output a second signal at a second voltage level higher than the first voltage level. A memory cell has a word line and a bit line. The word line is connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level, and the bit line is connected to the voltage input terminal to selectively receive the first signal at the first voltage level. A sense amplifier is connected to the bit line and is configured to provide an output of the memory cell. The sense amplifier has a sense amplifier input connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level.

Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

Abstract: A device for providing gated data signals includes a delay path configured to receive an input signal and output the input signal that is delayed from the input signal by a time interval; a gating signal generator configured to supply a gating signal; a gating circuit configured to receive the data signal from the delay path at the data input, receive the gating signal at the gating input, and output at the data output an output signal indicative of the received data signal when the gating signal is present at the gating input; and a delay controller configured to receive a variable delay control signal and set the delay time interval according to the delay control signal.

Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

Abstract: A turbine disc assembly is provided. The turbine disc assembly includes a first rotor disc, a second rotor disc, and a spacer disc coupled between the first and second rotor discs along an axis to define a plenum. The spacer disc has an inner surface with a radius from the axis. A first cooling channel defined between the first rotor disc and the spacer disc is in flow communication with the plenum. The second rotor disc includes a deflector having a deflection surface positioned within the plenum such that the deflection surface is oriented towards the first cooling channel at an acute angle relative to the radius of the inner surface of the spacer disc.

Abstract: A gas turbine casing with an internal heat exchange system. The gas turbine extends between an inlet section and an exhaust section and defines a downstream direction from the inlet section to the exhaust section. The casing includes a forward end, an aft end downstream of the forward end, a first exterior surface facing radially outward, a second exterior surface facing radially inward, and an internal body at least partially defined between the first exterior surface and the second exterior surface. The heat exchange system includes an inlet and an outlet formed in an exterior surface of the casing proximate the aft end, a supply bore extending upstream from the inlet through the interior body of the casing, and a return bore extending downstream to the outlet through the interior body of the casing.

Abstract: A device for providing gated data signals includes a delay path configured to receive an input signal and output the input signal that is delayed from the input signal by a time interval; a gating signal generator configured to supply a gating signal; a gating circuit configured to receive the data signal from the delay path at the data input, receive the gating signal at the gating input, and output at the data output an output signal indicative of the received data signal when the gating signal is present at the gating input; and a delay controller configured to receive a variable delay control signal and set the delay time interval according to the delay control signal.

Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

Abstract: A circuit is disclosed that includes an inverter unit and a switch unit. The inverter unit is coupled to a memory cell column. The inverter unit is configured to invert, in response to a first control signal and a second control signal, a first signal and to output a second signal for the enabling or disabling of a bit line keeper circuit that is configured to maintain a bit line to a voltage. The first signal is generated by the memory cell column. The switch unit is configured to couple a reference voltage to an input of the inverter unit, in response to a third control signal. The inverter unit is further configured to be deactivated in response to the reference voltage, the first control signal, and the second control signal.

Abstract: A circuit is disclosed that includes an inverter unit and a switch unit. The inverter unit is coupled to a memory cell column. The inverter unit is configured to invert, in response to a first control signal and a second control signal, a first signal and to output a second signal for the enabling or disabling of a bit line keeper circuit that is configured to maintain a bit line to a voltage. The first signal is generated by the memory cell column. The switch unit is configured to couple a reference voltage to an input of the inverter unit, in response to a third control signal. The inverter unit is further configured to be deactivated in response to the reference voltage, the first control signal, and the second control signal.

Abstract: An SRAM device has a voltage input terminal configured to receive a first signal at a first voltage level. A level shifter is connected to the voltage input terminal to receive the first signal, and the level shifter is configured to output a second signal at a second voltage level higher than the first voltage level. A memory cell has a word line and a bit line. The word line is connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level, and the bit line is connected to the voltage input terminal to selectively receive the first signal at the first voltage level. A sense amplifier is connected to the bit line and is configured to provide an output of the memory cell. The sense amplifier has a sense amplifier input connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level.

Abstract: A memory array having a first port and a second port is disclosed. The memory array includes: a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line; a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; and a disturb detector, used to generate a disturb detected signal for indicating whether the first memory cell and the second memory cell are accessed at a same time. A memory array having a write assistor is also disclosed.