Abstract: A memory array having a first port and a second port is disclosed. The memory array includes: a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line; a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; and a disturb detector, used to generate a disturb detected signal for indicating whether the first memory cell and the second memory cell are accessed at a same time. A memory array having a write assistor is also disclosed.

Abstract: A gas turbine casing with an internal heat exchange system. The gas turbine extends between an inlet section and an exhaust section and defines a downstream direction from the inlet section to the exhaust section. The casing includes a forward end, an aft end downstream of the forward end, a first exterior surface facing radially outward, a second exterior surface facing radially inward, and an internal body at least partially defined between the first exterior surface and the second exterior surface. The heat exchange system includes an inlet and an outlet formed in an exterior surface of the casing proximate the aft end, a supply bore extending upstream from the inlet through the interior body of the casing, and a return bore extending downstream to the outlet through the interior body of the casing.

Abstract: A turbine disc assembly is provided. The turbine disc assembly includes a first rotor disc, a second rotor disc, and a spacer disc coupled between the first and second rotor discs along an axis to define a plenum. The spacer disc has an inner surface with a radius from the axis. A first cooling channel defined between the first rotor disc and the spacer disc is in flow communication with the plenum. The second rotor disc includes a deflector having a deflection surface positioned within the plenum such that the deflection surface is oriented towards the first cooling channel at an acute angle relative to the radius of the inner surface of the spacer disc.

Abstract: A circuit detects values stored in bit cells of a memory circuit, for example, a memory circuit with single ended sensing. The circuit injects a charge into a bit line coupled to a bit cell to detect the value stored in the bit cell. A level detector detects the voltage level of the bitline as the charge in injected in the bitline. The sensing circuit determines the bit value stored during the charge injection phase. If the bitline voltage reaches above a high threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a first bit value (for example, bit value 1.) If the bitline voltage stays below a low threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a second bit value (for example, bit value 0).

Abstract: A circuit detects values stored in bit cells of a memory circuit, for example, a memory circuit with single ended sensing. The circuit injects a charge into a bit line coupled to a bit cell to detect the value stored in the bit cell. A level detector detects the voltage level of the bitline as the charge in injected in the bitline. The sensing circuit determines the bit value stored during the charge injection phase. If the bitline voltage reaches above a high threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a first bit value (for example, bit value 1.) If the bitline voltage stays below a low threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a second bit value (for example, bit value 0).

Abstract: The present subject matter relates to processing of Electrocardiogram (ECG) signals, and in particular, relates to identifying a QRS complex in an ECG signal. The method includes receiving, and filtering the ECG signal by passing through at least one of a first low-pass filter and a high-pass filter to obtain a filtered ECG signal. The filtered ECG signal is processed based on a moving average technique. Further, a search region is identified in the processed ECG signal, and a maximum amplitude peak is identified in a time interval of the filtered ECG signal that corresponds to a time span of the search region of the processed ECG signal. The maximum amplitude peak is an R peak of the QRS complex. Subsequently, a Q peak and an S peak of the QRS complex is identified based on the R peak.

Abstract: The present subject matter relates to processing of Electrocardiogram (ECG) signals, and in particular, relates to identifying a QRS complex in an ECG signal. The method includes receiving, and filtering the ECG signal by passing through at least one of a first low-pass filter and a high-pass filter to obtain a filtered ECG signal. The filtered ECG signal is processed based on a moving average technique. Further, a search region is identified in the processed ECG signal, and a maximum amplitude peak is identified in a time interval of the filtered ECG signal that corresponds to a time span of the search region of the processed ECG signal. The maximum amplitude peak is an R peak of the QRS complex. Subsequently, a Q peak and an S peak of the QRS complex is identified based on the R peak.

Abstract: Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in SoC device SRAM circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode). Alternatively, or in addition, source-biasing circuitry applies a relatively high source-biasing voltage to the source terminals of memory cells in unselected columns during read/write operations based on column address values (i.e., a low source voltage is applied only to the selected column being written to or read from).

Abstract: Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in SoC device SRAM circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode). Alternatively, or in addition, source-biasing circuitry applies a relatively high source-biasing voltage to the source terminals of memory cells in unselected columns during read/write operations based on column address values (i.e., a low source voltage is applied only to the selected column being written to or read from).

Abstract: A turbomachine includes a housing having an inner surface, a compressor, a turbine and a rotary member including a plurality of blade members configured as part of one of the compressor and the turbine. Each of the plurality of blade members includes a base portion and a tip portion. The turbomachine also includes a honeycomb seal member mounted to the inner surface of the housing adjacent the rotary member. The honeycomb seal member includes a contoured surface having formed therein a deformation zone. The deformation zone includes an inlet zone and an outlet zone. The inlet zone is spaced a first distance from the tip portion of each of the plurality of blade members and the outlet zone is spaced a second distance from the tip portion of each of the plurality of blade members. The second distance being substantially equal to or less than the first distance.

Abstract: An electronic device comprises a semiconductor memory cell having a bistable bit storage circuit having first and second power contact points. A first switch is coupled to the first power contact point to receive a first voltage. A second switch coupled to the second power contact point to receive a second voltage. Circuitry is provided for turning off the first and second switches to decouple the respective first and second voltages from the respective first and second power contact points, during stand-by operation of the electronic device.

Abstract: A seal system between a row of buckets supported on a machine rotor and a surrounding stationary casing or stator includes a tip shroud secured at radially outer tips of each of the buckets, the tip shroud formed with a radially-projecting rail. A cellular seal structure is supported in the stationary stator in radial opposition to the tip shroud and the rail. The seal structure has an annular array of individual cells formed to provide continuous, substantially horizontal flow passages devoid of any radial obstruction along substantially an entire axial length dimension of the cellular seal structure to prevent flow about the tip shroud from turning radially inwardly.

Abstract: A turbomachine includes a housing having an outer surface and an inner surface that defines an interior portion. The housing includes a fluid plenum. A rotating member is arranged within the housing. The rotating member includes at least one bucket having a base portion and a tip portion. A stationary member is mounted to the inner surface of the housing adjacent the tip portion of the at least one bucket. At least one fluid passage passes through at least a portion of the stationary member. The at least one fluid passage includes a fluid inlet fluidly coupled to the fluid plenum and a fluid outlet exposed to the interior portion. The fluid outlet being configured and disposed to direct a flow of fluid toward the tip portion of the at least one bucket.

Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.

Abstract: An apparatus is provided and includes a first member with a flow diverting member extending from a surface thereof and a second member disposed proximate to the first member with a clearance gap area defined between a surface of the second member and a distal end of the flow diverting member such that a fluid path, along which fluid flows from an upstream section and through the clearance gap area, is formed between the surfaces of the first and second members. The second member is formed to define dual vortex chambers at the upstream section in which the fluid is directed to flow in vortex patterns prior to being permitted to flow through the clearance gap area.

Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).

Abstract: A turbomachine includes a housing having an outer surface and an inner surface that defines an interior portion. The housing includes a fluid plenum. A rotating member is arranged within the housing. The rotating member includes at least one bucket having a base portion and a tip portion. A stationary member is mounted to the inner surface of the housing adjacent the tip portion of the at least one bucket. At least one fluid passage passes through at least a portion of the stationary member. The at least one fluid passage includes a fluid inlet fluidly coupled to the fluid plenum and a fluid outlet exposed to the interior portion. The fluid outlet being configured and disposed to direct a flow of fluid toward the tip portion of the at least one bucket.

Abstract: A turbine bucket for use with a turbine engine. The turbine bucket includes a dovetail that is coupled to a rotor assembly that is positioned within a turbine casing. A platform extends from the dovetail. An airfoil extends from the platform. The airfoil includes a root end and a tip end. The tip end extends outwardly from the root end towards the turbine casing. A tip shroud extends from the tip end. The tip shroud includes a shroud plate. A first shroud rail extending a first radial distance from the shroud plate towards the turbine casing. A second shroud rail extends a second radial distance from the shroud plate towards the turbine casing that is different than the first radial distance.

Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).

Abstract: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.