Patents by Inventor Sanjeev Sapra

Sanjeev Sapra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088211
    Abstract: Methods, apparatuses, and systems related to an over-sculpted storage node are described. An example method includes forming an opening in a pattern of materials. The method further includes performing an etch to over-sculpt the opening. The method further includes depositing a storage node material in the over-sculpted opening to form an over-sculpted storage node. The method further includes performing an etch to remove portions of the pattern of materials. The method further includes performing an etch on the storage node material to trim the over-sculpted storage node.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Devesh Dadhich Shreeram, Sanjeev Sapra, Kangle Li, Sevim Korkmaz
  • Publication number: 20230354585
    Abstract: Methods, apparatuses, and systems related to a digit line and cell contact are described. An example apparatus includes a semiconductor structure comprising a first layer comprising a first material on sidewalls of a plurality of patterned material. The apparatus further includes a second layer comprising a nitride material on sidewalls of the first layer. The apparatus further includes a third layer comprising the first material on sidewalls of the second layer. The apparatus further includes a base area, to provide digit line and cell contact isolation for the semiconductor structure. The apparatus further includes an active area, adjacent to the base area, that is adjacent to the semiconductor structure.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Inventors: Albert P. Chan, Sanjeev Sapra, Vivek Yadav, Yen Ting Lin, Devesh Dadhich Shreeram
  • Patent number: 11651952
    Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael T. Andreas, Jerome A. Imonigie, Prashant Raghu, Sanjeev Sapra, Ian K. McDaniel
  • Patent number: 11469103
    Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nicholas R. Tapias, Sanjeev Sapra, Anish A. Khandekar, Shen Hu
  • Publication number: 20220238532
    Abstract: A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 28, 2022
    Inventors: Devesh Dadhich Shreeram, Kangle Li, Matthew N. Rocklein, Wei Ching Huang, Ping-Cheng Hsu, Sevim Korkmaz, Sanjeev Sapra, An-Jen B. Cheng
  • Patent number: 11361972
    Abstract: Some embodiments include a method in which an assembly is formed to have a first silicon-dioxide-containing-material and a second silicon-dioxide-containing-material. The first silicon-dioxide-containing-material has a higher concentration of dopant therein than does the second silicon-dioxide-containing-material. The first silicon-dioxide-containing-material is selectively removed relative to the second silicon-dioxide-containing-material using a mixture which includes hydrofluoric acid, a second acid and an organic solvent. The organic solvent may include at least one ester and/or at least one ether. The second acid may have a pKa of less than about 5.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Ramaswamy Ishwar Venkatanarayanan, Pranav P. Sharma, Eric E. Kron, Sanjeev Sapra
  • Patent number: 11322388
    Abstract: An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vivek Yadav, Shen Hu, Kangle Li, Sanjeev Sapra
  • Patent number: 11127588
    Abstract: Methods, apparatuses, and systems related to semiconductor processing (e.g., of a capacitor support structure) are described. An example method includes patterning a surface of a semiconductor substrate to have a first silicate material, a nitride material over the first silicate material, and a second silicate material over the nitride material. The method further includes removing the first silicate material and the second silicate material and leaving the nitride material as a support structure for a column formed from a capacitor material. The method further includes performing supercritical drying on the column, after removal of the first and second silicate materials, to reduce a probability of the column wobbling relative to otherwise drying the column after the removal of the first and second silicate materials.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sevim Korkmaz, Sanjeev Sapra, Jerome A. Imonigie, Armin Saeedi Vahdat
  • Patent number: 11114443
    Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vivek Yadav, Fatma Arzum Simsek-Ege, Sanjeev Sapra, Thomas A. Figura, Kangle Li
  • Publication number: 20210159069
    Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.
    Type: Application
    Filed: February 5, 2021
    Publication date: May 27, 2021
    Inventors: Michael T. Andreas, Jerome A. Imonigie, Prashant Raghu, Sanjeev Sapra, Ian K. McDaniel
  • Patent number: 11011521
    Abstract: Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sevim Korkmaz, Devesh Dadhich Shreeram, Srinivasan Balakrishnan, Dewali Ray, Sanjeev Sapra, Paul A. Paduano
  • Patent number: 11011523
    Abstract: Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Devesh Dadhich Shreeram, Diem Thy N. Tran, Sanjeev Sapra
  • Publication number: 20210143011
    Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.
    Type: Application
    Filed: January 21, 2021
    Publication date: May 13, 2021
    Inventors: Nicholas R. Tapias, Sanjeev Sapra, Anish A. Khandekar, Shen Hu
  • Patent number: 10978306
    Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Adriel Jebin Jacob Jebaraj, Brian J. Kerley, Sanjeev Sapra, Ashwin Panday
  • Patent number: 10978553
    Abstract: Methods, apparatuses, and systems related to forming a capacitor using a hard mask material are described. An example method includes patterning a surface to have a first silicate material, a first nitride material on the first silicate material, a second silicate material on the first nitride material, a second nitride material on the second silicate material, and a sacrificial material on the second nitride material. The method further includes forming a hard mask material on the sacrificial material. The method further includes forming a capacitor material in an opening through the first silicate material, the first nitride material, the second silicate material, the second nitride material, the sacrificial material, and the hard mask material. The method further includes removing the sacrificial material and the hard mask material.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Diem Thy N. Tran, Devesh Dadhich Shreeram, Sanjeev Sapra
  • Patent number: 10964475
    Abstract: Methods, apparatuses, and systems related to forming a capacitor using a sacrificial material are described. An example method includes forming a first silicate material on a substrate. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes forming a column of capacitor material through the first silicate material, the first nitride material, the second silicate material, the second nitride material, and the sacrificial material. The method further includes removing the sacrificial material to expose a top portion of the capacitor material.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Devesh Dadhich Shreeram, Sevim Korkmaz, Jian Li, Sanjeev Sapra, Dewali Ray
  • Publication number: 20210066307
    Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Inventors: Vivek Yadav, Fatma Arzum Simsek-Ege, Sanjeev Sapra, Thomas A. Figura, Kangle Li
  • Publication number: 20210057266
    Abstract: An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Vivek Yadav, Shen Hu, Kangle Li, Sanjeev Sapra
  • Patent number: 10930499
    Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Nicholas R. Tapias, Sanjeev Sapra, Anish A. Khandekar, Shen Hu
  • Patent number: 10916418
    Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael T. Andreas, Jerome A. Imonigie, Prashant Raghu, Sanjeev Sapra, Ian K. McDaniel