Patents by Inventor Sanjeev Trika

Sanjeev Trika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12260126
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: March 25, 2025
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Peng Li, Jawad Khan, Jackson Ellis, Sanjeev Trika
  • Patent number: 12253945
    Abstract: Systems, apparatuses and methods may provide for technology that detects, via a processor external to a solid state drive (SSD), internal information associated with the SSD, detects background operations with respect to the SSD based on the internal information, wherein the background operations include one or more of current operations or predicted operations, and adjusts a hierarchical data placement policy based on the background operations.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: March 18, 2025
    Assignee: Intel Corporation
    Inventors: Sanjeev Trika, Piotr Wysocki
  • Patent number: 12118240
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Benjamin Walker, Sanjeev Trika, Kapil Karkra, James R. Harris, Steven C. Miller, Bishwajit Dutta
  • Patent number: 12093563
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: September 17, 2024
    Assignee: Intel Corporation
    Inventors: Kapil Karkra, Mariusz Barczak, Michal Wysoczanski, Sanjeev Trika, James Guilmart
  • Publication number: 20240264774
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 27, 2024
    Publication date: August 8, 2024
    Inventors: Peng Li, Jawad Khan, Jackson Ellis, Sanjeev Trika
  • Publication number: 20240241792
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Patent number: 12019910
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 25, 2024
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Peng Li, Jawad Khan, Jackson Ellis, Sanjeev Trika
  • Patent number: 11971782
    Abstract: Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 30, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20230082403
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 20, 2020
    Publication date: March 16, 2023
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20230027351
    Abstract: Systems, apparatuses and methods may provide for technology that includes a single server to store a portion of a temporal graph to a first memory of the single server, and store a second portion of the temporal graph to a second memory of the single server, wherein an access rate of the first memory is greater than an access rate of the second memory, and wherein a capacity of the second memory is greater than a capacity of the first memory. The single server may also retrieve vertices of the second portion in response to a selectivity of an input query exceeding a cost model threshold.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 26, 2023
    Inventors: Joana Matos Fonseca da Trindade, Jawad Khan, Sanjeev Trika
  • Patent number: 11461036
    Abstract: Technologies for logging and visualizing trace capture data in a data storage subsystem (e.g., storage application layers and data storage devices of a compute device) are disclosed herein. One or more storage events in the data storage subsystem are captured for a specified time period. Statistics are determined from the captured storage events. A visualization of the storage events and statistics for the specified time period is generated.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventor: Sanjeev Trika
  • Patent number: 11403044
    Abstract: In one embodiment, a storage device comprises non-volatile storage media; a controller to receive, from a host, an object definition command that identifies a first data object and a second data object and a transformation to apply to the first data object and the second data object to generate a first transformed object and store the first transformed object in the non-volatile storage media; and a transformation engine to apply the transformation to the first data object and the second data object.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Jawad Basit Khan, Peng Li, Sanjeev Trika
  • Publication number: 20220188228
    Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a two level memory controller mode that uses a dynamic random access memory as a transparent cache for a persistent memory. For example, a memory controller includes logic to map cached data in the dynamic random access memory to an original address of copied data in the persistent memory. The cached data in the dynamic random access memory is tracked as to whether it is dirty data or clean data with respect to the copied data in the persistent memory. Upon eviction of the cached data from the dynamic random access memory, a writeback of the cached data that has been evicted to the persistent memory is bypassed when the cached data is tracked as dirty data.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Sanjeev Trika, Mark Hildebrand, Jawad Khan
  • Publication number: 20220107733
    Abstract: An embodiment of an electronic apparatus may comprise a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory to determine a group of available types of persistent memory devices and a set of characteristics associated with each type of persistent memory device of the group of available types of persistent memory devices, determine of a set of requirements for a storage system, and determine a deployment configuration for the storage system with a lowest storage acquisition cost based on the group of available types of persistent memory devices, the sets of characteristics, and the set of requirements. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Applicant: Intel Corporation
    Inventors: Sanjeev Trika, Kapil Karkra, Mariusz Barczak
  • Publication number: 20210405889
    Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and circuitry coupled to the one or more substrates, the circuitry to track transactions that access a first memory level of a multi-level memory, control access to at least the first memory level of the multi-level memory, and control a roll back of at least the first memory level of the multi-level memory based on the tracked transactions. In another embodiment, the circuitry is to control a roll back of a multi-level memory in response to a request to roll back the multi-level memory. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventor: Sanjeev Trika
  • Publication number: 20210389890
    Abstract: Systems, apparatuses and methods may provide for memory controller technology that detects an application function, a data specifier associated with the application function, and one or more operating parameters associated with the application function, generates execution estimates for a plurality of computational storage devices based on the application function, the data specifier, the operating parameter(s), and one or more device capabilities associated with the plurality of computational storage devices, and selects a target storage device from the plurality of storage devices based on the execution estimates.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Inventor: Sanjeev Trika
  • Publication number: 20210342103
    Abstract: In one embodiment, a storage device comprises non-volatile storage media; a controller to receive, from a host, an object definition command that identifies a first data object and a second data object and a transformation to apply to the first data object and the second data object to generate a first transformed object and store the first transformed object in the non-volatile storage media; and a transformation engine to apply the transformation to the first data object and the second data object.
    Type: Application
    Filed: April 19, 2021
    Publication date: November 4, 2021
    Inventors: Jawad Basit Khan, Peng Li, Sanjeev Trika
  • Patent number: 11137916
    Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Michael Mesnier, Kapil Karkra, Piotr Wysocki, Jonathan Hughes, Brennan Watt, Sanjeev Trika, Anand Ramalingam
  • Publication number: 20210279007
    Abstract: Systems, apparatuses and methods may provide for controller technology that detects an application function, selects a target storage device from a plurality of storage devices including a first storage device and a second storage device that operates more slowly than the first storage device, and issue the application function to the target storage device. Additionally, storage device technology may identify data that is not present on non-volatile memory (NVM) of the storage device, generate an instruction to retrieve the data, and send the instruction to an external controller.
    Type: Application
    Filed: May 6, 2021
    Publication date: September 9, 2021
    Inventor: Sanjeev Trika
  • Publication number: 20210255955
    Abstract: Systems, apparatuses and methods may provide for technology that detects, via a processor external to a solid state drive (SSD), internal information associated with the SSD, detects background operations with respect to the SSD based on the internal information, wherein the background operations include one or more of current operations or predicted operations, and adjusts a hierarchical data placement policy based on the background operations.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Inventors: Sanjeev Trika, Piotr Wysocki