Patents by Inventor Sanjeev Trika

Sanjeev Trika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190042232
    Abstract: Technologies for automatic compilation of storage offloads include a compute device. The compute device further includes a compiler logic unit to analyze a source code of an application, identify a section of the source code that includes operations to be offloaded to a data storage device on a target compute device, extract, in response to an identification of the section that includes operations to be offloaded, the section of the source code, and compile the section of the source code extracted as an offload function.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Inventor: Sanjeev Trika
  • Publication number: 20190042113
    Abstract: An embodiment of a semiconductor apparatus may include technology to determine a persistent region and a non-persistent region of a volatile media based on an amount of power available from one or more backup power sources, and periodically backup only the non-persistent region of the volatile media to a non-volatile media. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Peng Li, Sanjeev Trika, Jawad Khan, Myron Loewen
  • Publication number: 20190042143
    Abstract: Technologies for logging and visualizing trace capture data in a data storage subsystem (e.g., storage application layers and data storage devices of a compute device) are disclosed herein. One or more storage events in the data storage subsystem are captured for a specified time period. Statistics are determined from the captured storage events. A visualization of the storage events and statistics for the specified time period is generated.
    Type: Application
    Filed: September 26, 2018
    Publication date: February 7, 2019
    Inventor: Sanjeev Trika
  • Publication number: 20190042142
    Abstract: An embodiment of a semiconductor apparatus may include technology to monitor one or more external performance indicators related to a workload impact on a persistent storage media, monitor one or more internal performance indicators for the persistent storage media, and adjust the workload based on the external performance indicators, the internal performance indicators, and priority information related to the workload. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 7, 2019
    Inventors: Jason Casmira, Jawad Khan, Ambika Krishnamoorthy, Sanjeev Trika
  • Publication number: 20190004737
    Abstract: In one embodiment, a storage device comprises non-volatile storage media; a controller to receive, from a host, an object definition command that identifies a first data object and a second data object and a transformation to apply to the first data object and the second data object to generate a first transformed object and store the first transformed object in the non-volatile storage media; and a transformation engine to apply the transformation to the first data object and the second data object.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Applicant: INTEL CORPORATION
    Inventors: Jawad Basit Khan, Peng Li, Sanjeev Trika
  • Publication number: 20190004768
    Abstract: One embodiment provides a storage device. The storage device includes a storage I/O (input/output) logic and a storage device controller. The storage I/O logic is to couple the storage device to a host device, the storage I/O logic to receive a sort-merge command the host device. The a storage device controller is to identify a level N SSTable (sorted string table) file, a corresponding level N index file, a first level N+1 SSTable file and a corresponding first level N+1 index file, in response to the sort-merge command to be received from the host device. The storage device controller is further to perform a sort-merge of the level N SSTable file and the first level N+1 SSTable file to produce a first level N+1 output SSTable file and a first level N+1 output SSTable index file. The level N SSTable file includes at least one level N key-value (KV) pair. The level N+1 SSTable file includes at least one level N+1 key-value (KV) pair.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Peng LI, Jawad B. KHAN, Sanjeev TRIKA
  • Publication number: 20180189508
    Abstract: In one embodiment, a system comprises a processor to, in response to a determination that a write command is suspect, identify a logical address associated with the write command; and send a checkpoint command identifying the logical address to a storage device to preserve data stored in the storage device at a physical address associated with the logical address.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Xiaoning Li, Ravi L. Sahita, Benjamin W. Boyer, Sanjeev Trika, Adrian Pearson
  • Publication number: 20170357462
    Abstract: In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 14, 2017
    Applicant: Intel Corporation
    Inventors: Benjamin L. Walker, August A. Camber, Jonathan Bryan Stern, Sanjeev Trika, Richard P. Mangold, Jawad Basit Khan, Anand Ramalingam
  • Publication number: 20170285949
    Abstract: Technology for an apparatus is described. The apparatus can include a memory and a storage controller. The storage controller can be configured to receive a search command with one or more parameters that instructs the storage controller to search for a data pattern in data stored in the memory. The storage controller can be configured to search the data stored in the memory for the data pattern according to the one or more parameters included in the search command. The storage controller can be configured to locally search the data in the memory for the data pattern without transferring the data to a processor to perform the search.
    Type: Application
    Filed: April 2, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Sanjeev Trika, Kshitij Doshi
  • Patent number: 9530461
    Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Jason B. Akers, Knut S. Grimsrud, Robert J. Royer, Jr., Richard P. Mangold, Sanjeev Trika
  • Publication number: 20140003145
    Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: JASON B. AKERS, Knut S. Grimsrud, Robert J. Royer, JR., Richard P. Mangold, Sanjeev Trika
  • Publication number: 20070233947
    Abstract: In one embodiment, the present invention includes a method for maintaining a sequence of writes into a disk cache, where the writes correspond to disk write requests stored in the disk cache, and ordering cache writes from the disk cache to a disk drive according to the sequence of writes. In this way, write ordering from an operating system to a disk subsystem is maintained. Other embodiments are described and claimed.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 4, 2007
    Inventors: Richard Coulson, Sanjeev Trika, Jeanna Matthews, Robert Faber
  • Publication number: 20070168698
    Abstract: Write operations store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. Sequence information stored in the physical memory location indicates which one of the write operations occurred last. The available erased memory location can be split into a list of erased memory locations available to be used and a list of erased memory locations not available to be used. Then, on a failure, only the list of erased memory locations available to be used needs to be analyzed to reconstruct the consumption states of memory locations.
    Type: Application
    Filed: November 3, 2005
    Publication date: July 19, 2007
    Inventors: Richard Coulson, Sanjeev Trika, Robert Faber
  • Publication number: 20070156954
    Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 5, 2007
    Inventors: Sanjeev Trika, Michael Eschmann, Jeanna Matthews, Vasudevan Srinivasan
  • Publication number: 20070156955
    Abstract: A method includes receiving a request to access a disk drive. The request has a size. The method further includes selecting a queue, based at least in part on the size of the request, from among a plurality of queues, and assigning the request to the selected queue.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Robert Royer, Michael Eschmann, Amber Huffman, Knut Grimsrud, Sanjeev Trika, Brian Dees
  • Publication number: 20070094445
    Abstract: The above-described methods and computer system describe the use of dynamic addressing, lazy relocations and erases, and page state information to provide fast disk caching and solid state disk applications using solid-state nonvolatile memories. The approach reduces write-latencies for demand requests, as well as the number of erase cycles on erase blocks.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventors: Sanjeev Trika, Robert Faber, Rick Coulson
  • Publication number: 20070038850
    Abstract: A system and method to reduce the time for system initializations is disclosed. For at least one embodiment, data accessed during a system initialization is loaded into a non-volatile cache during shutdown or entry into a low-power mode. On a subsequent boot, or resumption after a low power mode, the data required for system initialization has already been pre-loaded into the cache, thereby eliminating the need to access a disk. Other embodiments are also described and claimed.
    Type: Application
    Filed: August 10, 2005
    Publication date: February 15, 2007
    Inventors: Jeanna Matthews, Sanjeev Trika
  • Publication number: 20070005883
    Abstract: In some embodiments, a method to keep volatile disk caches warm across reboots is presented. In this regard, a caching agent is introduced to, responsive to a system boot, load a cache data from a reserved portion of a mass storage device into a memory. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventor: Sanjeev Trika
  • Publication number: 20070005928
    Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Sanjeev Trika, Robert Faber, Rick Coulson, Jeanna Matthews
  • Publication number: 20060294339
    Abstract: Embodiments of abstracted dynamic addressing are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Sanjeev Trika, Robert Royer, John Garney, Richard Mangold