Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.

Abstract: A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is sufficiently etch-selective with respect to the first material, and then performing a wet etch to remove most of the first material but not the second material, thus forming a cavity within the second material. Shape and dimensions of the cavity are comparable to those desired for the final non-planar capacitor. At least one electrode of a capacitor may then be formed within the cavity. Using the etch selectivity of the first and second materials advantageously allows applying wet etch techniques for forming high aspect ratio openings in fabricating non-planar capacitors, which is easier and more reliable than relying on dry etch techniques.

Abstract: Modern RF front end filters feature acoustic resonators in a film bulk acoustic resonator (FBAR) structure. An acoustic filter is a circuit that includes at least (and typically significantly more) two resonators. The acoustic resonator structure comprises a substrate including sidewalls and a vertical cavity between the sidewalls and two or more resonators deposited in the vertical cavity.

Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

Abstract: Technologies for thermoelectric enhanced cooling on an integrated circuit die are disclosed. In the illustrative embodiment, one or more components are created on a top side of an integrated circuit die, such as a power amplifier, logic circuitry, etc. The one or more components, in use, generate heat that needs to be carried away from the components. A thermoelectric cooler can be created on a back side of the die in order to facilitate removal of heat from the component. In some embodiments, additional structures such as vias filled with high-thermal-conductivity material may be used to further improve the removal of heat from the component.

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

Abstract: In one embodiment, an integrated circuit includes a silicon substrate, a gallium nitride (GaN) layer above the silicon substrate, a bonding layer above the GaN layer, and a silicon layer above the bonding layer. Further, the integrated circuit includes a first transistor on the GaN layer and a second transistor on the silicon layer.

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.

Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.

Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.

Abstract: A method for forming III-N structures of desired nanoscale dimensions is disclosed. The method is based on, first, providing a material to serve as a shell inside which a cavity can be formed, followed by using epitaxial growth to fill the cavity with III-N semiconductor(s). Filling a cavity of specified shape and dimensions with a III-N semiconductor results in formation of a III-N structure which has shape and dimensions defined by those of the cavity in the shell, advantageously enabling formation of III-N structures on a nanometer scale without having to rely on etching of III-N materials. Ensuring that at least a part of the III-N material in the cavity is formed by lateral epitaxial overgrowth allows obtaining high quality III-N semiconductor in that part without having to grow a thick layer. Disclosed III-N nanostructures can serve as foundation for fabricating III-N device components, e.g. III-N transistors, having non-planar architecture.

Abstract: Integrated circuits with III-N metal-insulator-semiconductor field effect transistor (MISFET) structures that employ one or more gate dielectric materials that differ across the MISFETs. Gate dielectric materials may be selected to modulate dielectric breakdown strength and/or threshold voltage between transistors. Threshold voltage may be modulated between two MISFET structures that may be substantially the same but for the gate dielectric. Control of the gate dielectric material may render some MISFETs to be operable in depletion mode while other MISFETs are operable in enhancement mode. Gate dielectric materials may be varied by incorporating multiple dielectric materials in some MISFETs of an IC while other MISFETs of the IC may include only a single dielectric material. Combinations of gate dielectric material layers may be selected to provide a menu of low voltage, high voltage, enhancement and depletion mode MISFETs within an IC.

Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor. Ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.

Abstract: Micro light-emitting diode (LED) displays, and fabrication and assembly of micro LED displays, are described. In an example, a pixel element for a micro-light emitting diode (LED) display panel includes a blue color nanowire or nanopyramid LED above a first nucleation layer above a substrate, the blue color nanowire or nanopyramid LED including a first GaN core. A green color nanowire or nanopyramid LED is above a second nucleation layer above the substrate, the green color nanowire or nanopyramid LED including a second GaN core. A red color nanowire or nanopyramid LED is above a third nucleation layer above the substrate, the red color nanowire or nanopyramid LED including a GaInP core.

Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

Abstract: In one embodiment, an integrated circuit die includes a substrate, a base structure, and a plurality of semiconductor structures. The substrate includes silicon. The base structure is above the substrate and includes one or more group III-nitride (III-N) materials. The semiconductor structures are in a two-dimensional (2D) layout on the base structure and include a plurality of metal contacts, at least some of which have different shapes and comprise different metals.

Abstract: An integrated circuit film bulk acoustic resonator (FBAR) device having multiple resonator thicknesses is formed on a common substrate in a stacked configuration. In an embodiment, a seed layer is deposited on a substrate, and one or more multi-layer stacks are deposited on the seed layer, each multi-layer stack having a first metal layer deposited on a first sacrificial layer, and a second metal layer deposited on a second sacrificial layer. The second sacrificial layer can be removed and the resulting space is filled in with a piezoelectric material, and the first sacrificial layer can be removed to release the piezoelectric material from the substrate and suspend the piezoelectric material above the substrate. More than one multi-layer stack can be added, each having a unique resonant frequency. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate.

Abstract: Gallium nitride (GaN) layer transfer for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A first layer including gallium and nitrogen is over a first region of the substrate, the first layer having a gallium-polar orientation with a top crystal plane consisting of a gallium face. A second layer including gallium and nitrogen is over a second region of the substrate, the second layer having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.