Patents by Inventor Sansaptak DASGUPTA

Sansaptak DASGUPTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11610887
    Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a TFT provided over a second portion of the III-N material. Because the III-N transistor and the TFT are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the TFT are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration. Integrating TFTs with III-N transistors may reduce costs and improve performance, e.g., by reducing losses incurred when power is routed off chip in a multi-chip package.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
  • Patent number: 11610971
    Abstract: An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Nidhi Nidhi, Rahul Ramaswamy, Johann Rode, Paul Fischer, Walid Hafez
  • Publication number: 20230068318
    Abstract: Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×1017 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 1017 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Intel Corporation
    Inventors: Richard Geiger, Georgios Panagopoulos, Luis Felipe Giles, Peter Baumgartner, Harald Gossner, Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then
  • Patent number: 11588037
    Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
  • Patent number: 11587862
    Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 21, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Sanaz K. Gardner
  • Patent number: 11581313
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Sandrine Charue-Bakker, Walid M. Hafez
  • Patent number: 11575036
    Abstract: Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Stephan Leuschner, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11563098
    Abstract: A transistor is disclosed. The transistor includes a first part of a gate above a substrate that has a first width and a second part of the gate above the first part of the gate that is centered with respect to the first part of the gate and that has a second width that is greater than the first width. The first part of the gate and the second part of the gate form a single monolithic T-gate structure.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul Fischer
  • Patent number: 11558032
    Abstract: A bulk acoustic resonator architecture is fabricated by epitaxially forming a piezoelectric film on a top surface of post formed from an underlying substrate. In some cases, the acoustic resonator is fabricated to filter multiple frequencies. In some such cases, the resonator device includes two different resonator structures on a single substrate, each resonator structure configured to filter a desired frequency. Including two different acoustic resonators in a single RF acoustic resonator device enables that single device to filter two different frequencies in a relatively small footprint.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Bruce A. Block, Paul B. Fischer, Han Wui Then, Marko Radosavljevic
  • Patent number: 11557667
    Abstract: A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Ibrahim Ban, Paul B. Fischer
  • Patent number: 11552075
    Abstract: A device includes a diode that includes a first group III-nitride (III-N) material and a transistor adjacent to the diode, where the transistor includes the first III-N material. The diode includes a second III-N material, a third III-N material between the first III-N material and the second III-N material, a first terminal including a metal in contact with the third III-N material, a second terminal coupled to the first terminal through the first group III-N material. The device further includes a transistor structure, adjacent to the diode structure. The transistor structure includes the first, second, and third III-N materials, a source and drain, a gate electrode and a gate dielectric between the gate electrode and each of the first, second and third III-N materials.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: January 10, 2023
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul Fischer, Walid Hafez
  • Patent number: 11545586
    Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11538804
    Abstract: Disclosed herein are integrated circuit (IC) structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. One example IC structure includes an III-N transistor in a first layer over a support structure (e.g., a substrate) and a TFT in a second layer over the support structure, where the first layer is between the support structure and the second layer. Another example IC structure includes a III-N semiconductor material and a TFT, where at least a portion of a channel material of the TFT is over at least a portion of the III-N semiconductor material.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
  • Patent number: 11538901
    Abstract: Techniques are disclosed for forming an integrated circuit including a capacitor having a multilayer dielectric stack. For example, the capacitor may be a metal-insulator-metal capacitor (MIMcap), where the stack of dielectric layers is used for the insulator or ‘I’ portion of the MIM structure. In some cases, the composite or multilayer stack for the insulator portion of the MIM structure may include a first oxide layer, a dielectric layer, a second oxide layer, and a high-k dielectric layer, as will be apparent in light of this disclosure. Further, the multilayer dielectric stack may include an additional high-k dielectric layer, for example. Use of such multilayer dielectric stacks can enable increases in capacitance density and/or breakdown voltage for a MIMcap device. Further, use of a multilayer dielectric stack can enable tuning of the breakdown and capacitance characteristics as desired. Other embodiments may be described and/or disclosed.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 11527610
    Abstract: An integrated circuit structure comprises a silicon substrate and a III-nitride (III-N) substrate over the silicon substrate. A first III-N transistor and a second III-N transistor is on the III-N substrate. An insulator structure is formed in the III-N substrate between the first III-N transistor and the second III-N, wherein the insulator structure comprises one of: a shallow trench filled with an oxide, nitride or low-K dielectric; or a first gap adjacent to the first III-N transistor and a second gap adjacent to the second III-N transistor.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then
  • Patent number: 11527532
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Patent number: 11521964
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Paul Fischer, Walid Hafez, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11515407
    Abstract: An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack is located over over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Glenn Glass, Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Paul Fischer, Anand Murthy, Walid Hafez
  • Patent number: 11515402
    Abstract: The present description relates to the fabrication of microelectronic transistor source and/or drain regions using angled etching. In one embodiment, a microelectronic transistor may be formed by using an angled etch to reduce the number masking steps required to form p-type doped regions and n-type doped regions. In further embodiments, angled etching may be used to form asymmetric spacers on opposing sides of a transistor gate, wherein the asymmetric spacers may result in asymmetric source/drain configurations.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Robert B. Turkot, Marko Radosavljevic, Han Wui Then, Willy Rachmady, Sansaptak Dasgupta, Jack T. Kavalieros
  • Patent number: 11508812
    Abstract: Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Pavel M. Agababov