Patents by Inventor Santosh Ghosh

Santosh Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12032486
    Abstract: In one embodiment, a processor includes circuitry to decode an instruction referencing an encoded data pointer that includes a set of plaintext linear address bits and a set of encrypted linear address bits. The processor also includes circuitry to perform a speculative lookup in a translation lookaside buffer (TLB) using the plaintext linear address bits to obtain physical address, buffer a set of architectural predictor state values based on the speculative TLB lookup, and speculatively execute the instruction using the physical address obtained from the speculative TLB lookup. The processor also includes circuitry to determine whether the speculative TLB lookup was correct and update a set of architectural predictor state values of the core using the buffered architectural predictor state values based on a determination that the speculative TLB lookup was correct.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 9, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek Basak, Santosh Ghosh, Michael D. LeMay, David M. Durham
  • Publication number: 20240223381
    Abstract: Techniques for performing digital signature verification are described. Digital signature verification circuitry includes a memory; and signature verification circuitry, including Secure Hash Algorithm (SHA) circuitry; message representative generator circuitry; tree verification circuitry; and hypertree verification circuitry.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Alan Hwang, Solmaz Ghaznavi, Santosh Ghosh
  • Publication number: 20240220640
    Abstract: In one example an apparatus comprises a first input node to receive a first input bit, an encryption circuit to split the first input bit into a first share and a second share, and perform an encryption function on the first input share and the second input share to generate a first output share and a second output share, an error tag generator circuit to calculate a first error tag from the first input share and the second input share, and calculate a second error tag from the first output share and the second output share, an error detection circuit to generate an error signal when the first error tag does not match the second error tag.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Daniƫl Kuijsters, Christoph Dobraunig, Santosh Ghosh
  • Patent number: 12026516
    Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rot
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: July 2, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry
  • Publication number: 20240211261
    Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rot
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry
  • Publication number: 20240211268
    Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry
  • Publication number: 20240211253
    Abstract: A method comprises fetching, by fetch circuitry, an encoded parity instruction comprising at least one opcode, a first source identifier for a first source, a second source identifier for a second source, a third source identifier for a third source, and a destination identifier for a destination, decoding, by decode circuitry, the encoded parity instruction to generate a decoded parity instruction; and executing, by execution circuitry, the decoded parity instruction to retrieve operands representing a first register from the first source, a second register from the second source, a third register from the third source, and an index from the third source, perform an XOR operation of four words of data from the first register and single word of data from the second register in a position represented by the index to generate a parity value, and store the parity value in a the first register in a position represented by the index.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry, Andrew H. Reinders, Regev Shemy, Qian Wang, Rotem Ohana Peretz, Wing Shek Wong, Wajdi Feghali
  • Publication number: 20240179160
    Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.
    Type: Application
    Filed: December 1, 2023
    Publication date: May 30, 2024
    Applicant: Intel Corporation
    Inventors: Marcio Rogerio Juliato, Shabbir Ahmed, Santosh Ghosh, Christopher Gutierrez, Manoj R. Sastry
  • Patent number: 11995184
    Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 28, 2024
    Assignee: INTEL CORPORATION
    Inventors: Santosh Ghosh, Andrea Basso, Manoj Sastry
  • Patent number: 11985226
    Abstract: An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a ? step of a SHA calculation, a second section to perform a ? step and a ? step of the SHA calculation, a third section to perform a ? step of the SHA calculation and a fourth section to perform a ? step of the SHA calculation.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Marcio Juliato, Manoj Sastry
  • Patent number: 11954045
    Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: David M. Durham, Michael LeMay, Santosh Ghosh, Sergej Deutsch
  • Publication number: 20240113888
    Abstract: In one example an apparatus comprises processing circuitry to measure a statistical distance between a marginal distribution of a coordinate of a potential signature (z) over a first interval and a uniform distribution over the first interval and use the statistical distance to determine one or more thresholds of a rejection sampling operation in a lattice-based digital signature algorithm. Other examples may be described.
    Type: Application
    Filed: September 28, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: ZACHARY PEPIN, SANTOSH GHOSH, MANOJ SASTRY
  • Publication number: 20240106628
    Abstract: A system and method for generating, from a permutation of a first input state, a first output state, a first rate and a first capacity, the first rate including a first portion of the first output state and the first capacity including a second portion of the first output state; storing the first output state; generating a first block of ciphertext data of a first packet from XORing the first rate and a first block of plaintext data of the first packet; generating a permutation of a value of the first block of ciphertext data of the first packet concatenated with the first capacity, and generating a second block of ciphertext data of the first packet from XOR of the permutation of the value of the first block of ciphertext data of the first packet concatenated with the first capacity.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventor: Santosh Ghosh
  • Publication number: 20240104027
    Abstract: In one embodiment, a processor includes a cache and a core. The core includes an execution unit and cryptographic computing circuitry to encrypt plaintext data output by the execution unit and store the encrypted data in the cache and decrypt encrypted data accessed from the cache and provide the decrypted data to the execution unit for processing. The encryption and decryption are based on both a stream cipher and a block cipher. In some embodiments, the encryption is based on providing an output of the stream cipher to the block cipher and the decryption is based on providing an output of the block cipher to the stream cipher.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Christoph Dobraunig, Michael LeMay, David M. Durham
  • Patent number: 11940888
    Abstract: A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a processing core and a fault-tolerant elliptic curve digital signature algorithm (ECDSA) engine. The fault-tolerant ECDSA engine comprises multiple verification state machines (VSMs). The data processing system also comprises nonvolatile storage in communication with the processing core and ECU software in the nonvolatile storage. The ECU software, when executed, enables the data processing system to operate as a node in a distributed data processing system, including receiving digitally signed messages from other nodes in the distributed data processing system. The ECU further comprises a known-answer built-in self-test unit (KA-BISTU). Also, the ECU software comprises fault-tolerant ECDSA engine (FTEE) management software which, when executed by the processing core, utilizes the KA-BISTU to periodically test the fault-tolerant ECDSA engine for faults.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: March 26, 2024
    Assignee: INTEL CORPORATION
    Inventors: Santosh Ghosh, Marcio Juliato, Manoj R. Sastry
  • Patent number: 11917053
    Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
  • Patent number: 11909857
    Abstract: Systems, apparatus, methods, and techniques for functional safe execution of encryption operations are provided. A fault tolerant counter and a complementary pair of encryption flows are provided. The fault tolerant counter may be based on a gray code counter and a hamming distance checker. The complementary pair of encryption flows have different implementations. The output from the complementary pair of encryption flows can be compared, and where different, errors generated.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Marcio Juliato, Rafael Misoczki, Manoj Sastry, Liuyang Yang, Shabbir Ahmed, Christopher Gutierrez, Xiruo Liu
  • Publication number: 20240031140
    Abstract: In one example an apparatus comprises a first input node to receive a first input, a second input node to receive a control signal, a polynomial multiplication circuitry to perform a polynomial multiplication operation using the first input in a security mode determined by the control signal, the security mode comprising one of a first mode in which no side-channel protection is provided to the polynomial multiplication operation, a second mode in which a shuffling-based side-channel protection is provided to the polynomial multiplication operation, a third mode in which a masking or splitting side-channel protection is provided to the polynomial multiplication operation, or a fourth mode in which a masking and shuffling based side-channel protection is provided to the polynomial multiplication operation. Other examples may be described.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Applicant: Intel Corporation
    Inventors: ANDREA BASSO, DUMITRU-DANIEL DINU, SANTOSH GHOSH, MANOJ SASTRY
  • Publication number: 20240031168
    Abstract: Various examples relate to an apparatus, device, method, and computer program for determining an integrity of a generated cryptographic signature. The apparatus is to generate, before generating the cryptographic signature, redundancy information of at least one cryptographic secret being used for generating the cryptographic signature, generate the cryptographic signature using the at least one cryptographic secret, compare, after generating the cryptographic signature, the redundancy information and the at least one cryptographic secret to determine whether the redundancy information matches the at least one cryptographic secret, and use the cryptographic signature if the redundancy information matches the at least one cryptographic secret.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Inventors: Yingchen WANG, Santosh GHOSH, Manoj SASTRY, Qian WANG, Lucian COJOCAR
  • Publication number: 20240031127
    Abstract: In one example an apparatus comprises a first input node to receive a first input, a second input node to receive a control signal, a polynomial multiplication circuitry to perform a polynomial multiplication function using the first input as an element of a digital signature protocol, the polynomial multiplication function comprising a plurality of polynomial multiplication operations, the polynomial multiplication function performed in a security mode determined by the control signal, the security mode comprising one of a first mode in which no side-channel protection is provided to the polynomial multiplication operation or a second mode in which a shuffling-based side-channel protection is provided to the polynomial multiplication operation. Other examples may be described.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Applicant: Intel Corporation
    Inventors: ANDREA BASSO, DUMITRU-DANIEL DINU, SANTOSH GHOSH, MANOJ SASTRY