Patents by Inventor Santosh Ghosh
Santosh Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12058261Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.Type: GrantFiled: September 21, 2021Date of Patent: August 6, 2024Assignee: INTEL CORPORATIONInventors: Santosh Ghosh, Andrea Basso, Dumitru-Daniel Dinu, Avinash L. Varna, Manoj Sastry
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Publication number: 20240259182Abstract: Techniques for implementing Advanced Encryption Standard (AES)-256 encryption. An implementation includes a time-shared round data path with a depth-2 pipeline that results in an atomic execution of two 14-round AES-256 encryption operations in 30 cycles while operating at the same high-frequency clock used for processing cores of a computing system. The technology described herein uses only two cycles of latency per round while supporting a very high maximum operating clock speed.Type: ApplicationFiled: February 1, 2023Publication date: August 1, 2024Applicant: Intel CorporationInventor: Santosh Ghosh
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Patent number: 12050701Abstract: Technologies disclosed herein provide cryptographic computing. An example method comprises executing a first instruction of a first software entity to receive a first input operand indicating a first key associated with a first memory compartment of a plurality of memory compartments stored in a first memory unit, and execute a cryptographic algorithm in a core of a processor to compute first encrypted contents based at least in part on the first key. Subsequent to computing the first encrypted contents in the core, the first encrypted contents are stored at a memory location in the first memory compartment of the first memory unit. More specific embodiments include, prior to storing the first encrypted contents at the memory location in the first memory compartment and subsequent to computing the first encrypted contents in the core, moving the first encrypted contents into a level one (L1) cache outside a boundary of the core.Type: GrantFiled: June 6, 2022Date of Patent: July 30, 2024Assignee: Intel CorporationInventors: Michael E. Kounavis, Santosh Ghosh, Sergej Deutsch, Michael LeMay, David M. Durham
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Patent number: 12047514Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.Type: GrantFiled: April 29, 2022Date of Patent: July 23, 2024Assignee: Intel CorporationInventors: Santosh Ghosh, Manoj Sastry, Prakash Iyer, Ting Lu
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Patent number: 12032486Abstract: In one embodiment, a processor includes circuitry to decode an instruction referencing an encoded data pointer that includes a set of plaintext linear address bits and a set of encrypted linear address bits. The processor also includes circuitry to perform a speculative lookup in a translation lookaside buffer (TLB) using the plaintext linear address bits to obtain physical address, buffer a set of architectural predictor state values based on the speculative TLB lookup, and speculatively execute the instruction using the physical address obtained from the speculative TLB lookup. The processor also includes circuitry to determine whether the speculative TLB lookup was correct and update a set of architectural predictor state values of the core using the buffered architectural predictor state values based on a determination that the speculative TLB lookup was correct.Type: GrantFiled: December 23, 2021Date of Patent: July 9, 2024Assignee: Intel CorporationInventors: Abhishek Basak, Santosh Ghosh, Michael D. LeMay, David M. Durham
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Publication number: 20240223381Abstract: Techniques for performing digital signature verification are described. Digital signature verification circuitry includes a memory; and signature verification circuitry, including Secure Hash Algorithm (SHA) circuitry; message representative generator circuitry; tree verification circuitry; and hypertree verification circuitry.Type: ApplicationFiled: January 20, 2023Publication date: July 4, 2024Applicant: Intel CorporationInventors: Alan Hwang, Solmaz Ghaznavi, Santosh Ghosh
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Publication number: 20240220640Abstract: In one example an apparatus comprises a first input node to receive a first input bit, an encryption circuit to split the first input bit into a first share and a second share, and perform an encryption function on the first input share and the second input share to generate a first output share and a second output share, an error tag generator circuit to calculate a first error tag from the first input share and the second input share, and calculate a second error tag from the first output share and the second output share, an error detection circuit to generate an error signal when the first error tag does not match the second error tag.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Daniƫl Kuijsters, Christoph Dobraunig, Santosh Ghosh
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Patent number: 12026516Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rotType: GrantFiled: December 22, 2022Date of Patent: July 2, 2024Assignee: Intel CorporationInventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry
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Publication number: 20240211268Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generateType: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Applicant: Intel CorporationInventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry
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Publication number: 20240211261Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rotType: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Applicant: Intel CorporationInventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry
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Publication number: 20240211253Abstract: A method comprises fetching, by fetch circuitry, an encoded parity instruction comprising at least one opcode, a first source identifier for a first source, a second source identifier for a second source, a third source identifier for a third source, and a destination identifier for a destination, decoding, by decode circuitry, the encoded parity instruction to generate a decoded parity instruction; and executing, by execution circuitry, the decoded parity instruction to retrieve operands representing a first register from the first source, a second register from the second source, a third register from the third source, and an index from the third source, perform an XOR operation of four words of data from the first register and single word of data from the second register in a position represented by the index to generate a parity value, and store the parity value in a the first register in a position represented by the index.Type: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Applicant: Intel CorporationInventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry, Andrew H. Reinders, Regev Shemy, Qian Wang, Rotem Ohana Peretz, Wing Shek Wong, Wajdi Feghali
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Publication number: 20240179160Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.Type: ApplicationFiled: December 1, 2023Publication date: May 30, 2024Applicant: Intel CorporationInventors: Marcio Rogerio Juliato, Shabbir Ahmed, Santosh Ghosh, Christopher Gutierrez, Manoj R. Sastry
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Patent number: 11995184Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.Type: GrantFiled: September 24, 2021Date of Patent: May 28, 2024Assignee: INTEL CORPORATIONInventors: Santosh Ghosh, Andrea Basso, Manoj Sastry
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Patent number: 11985226Abstract: An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a ? step of a SHA calculation, a second section to perform a ? step and a ? step of the SHA calculation, a third section to perform a ? step of the SHA calculation and a fourth section to perform a ? step of the SHA calculation.Type: GrantFiled: December 23, 2020Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Santosh Ghosh, Marcio Juliato, Manoj Sastry
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Patent number: 11954045Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.Type: GrantFiled: September 24, 2021Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: David M. Durham, Michael LeMay, Santosh Ghosh, Sergej Deutsch
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Publication number: 20240113888Abstract: In one example an apparatus comprises processing circuitry to measure a statistical distance between a marginal distribution of a coordinate of a potential signature (z) over a first interval and a uniform distribution over the first interval and use the statistical distance to determine one or more thresholds of a rejection sampling operation in a lattice-based digital signature algorithm. Other examples may be described.Type: ApplicationFiled: September 28, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: ZACHARY PEPIN, SANTOSH GHOSH, MANOJ SASTRY
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Publication number: 20240106628Abstract: A system and method for generating, from a permutation of a first input state, a first output state, a first rate and a first capacity, the first rate including a first portion of the first output state and the first capacity including a second portion of the first output state; storing the first output state; generating a first block of ciphertext data of a first packet from XORing the first rate and a first block of plaintext data of the first packet; generating a permutation of a value of the first block of ciphertext data of the first packet concatenated with the first capacity, and generating a second block of ciphertext data of the first packet from XOR of the permutation of the value of the first block of ciphertext data of the first packet concatenated with the first capacity.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventor: Santosh Ghosh
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Publication number: 20240104027Abstract: In one embodiment, a processor includes a cache and a core. The core includes an execution unit and cryptographic computing circuitry to encrypt plaintext data output by the execution unit and store the encrypted data in the cache and decrypt encrypted data accessed from the cache and provide the decrypted data to the execution unit for processing. The encryption and decryption are based on both a stream cipher and a block cipher. In some embodiments, the encryption is based on providing an output of the stream cipher to the block cipher and the decryption is based on providing an output of the block cipher to the stream cipher.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Santosh Ghosh, Christoph Dobraunig, Michael LeMay, David M. Durham
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Patent number: 11940888Abstract: A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a processing core and a fault-tolerant elliptic curve digital signature algorithm (ECDSA) engine. The fault-tolerant ECDSA engine comprises multiple verification state machines (VSMs). The data processing system also comprises nonvolatile storage in communication with the processing core and ECU software in the nonvolatile storage. The ECU software, when executed, enables the data processing system to operate as a node in a distributed data processing system, including receiving digitally signed messages from other nodes in the distributed data processing system. The ECU further comprises a known-answer built-in self-test unit (KA-BISTU). Also, the ECU software comprises fault-tolerant ECDSA engine (FTEE) management software which, when executed by the processing core, utilizes the KA-BISTU to periodically test the fault-tolerant ECDSA engine for faults.Type: GrantFiled: September 14, 2021Date of Patent: March 26, 2024Assignee: INTEL CORPORATIONInventors: Santosh Ghosh, Marcio Juliato, Manoj R. Sastry
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Patent number: 11917053Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.Type: GrantFiled: March 29, 2022Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Santosh Ghosh, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki