Abstract: A system includes a memory die stack that provides sensing information via proxy. The memory die stack includes at least a first memory die with a sensor that generates sensing data for the first memory die and a second memory die with a sensor that generates sensing data for the second memory die. The proxy is a logic device that aggregates and sends the sensing data for both memory dies over a management communication bus.

Abstract: Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

Abstract: A memory subsystem allows the memory controller and the memory to create a trusted communication channel based on a certificate exchange. The memory and memory controller have a key storage to store the certificates. The memory controller can be restricted to only be enabled to access a system data storage array after the trusted communication channel is established.

Abstract: A configuration register update mode can be implemented as an MRUPD (mode register update) mode for a DRAM (dynamic random access memory) device. In one example, the MRUPD can also be applied to update an RCD (registering clock driver). In the update mode, the memory device (either the RCD or the DRAM) can perform configuration of any number of configuration registers with in-band register writes. The in-band register writes can be used to configure DFE (decision feedback equalization) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

Abstract: Training a physical interface between a memory device and a memory controller can be performed with an autonomous sweep. The sweep can occur without commands from the host to trigger each parameter sweep. With a two dimensional sweep, instead of interrupting a training mode for a first parameter to sweep a second parameter, circuitry in the memory can automatically sweep the second parameter in the training mode for the first parameter.

Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.

Abstract: A configuration register update mode can be implemented as a register word update (RWUPD) mode for a registering clock driver (RCD) or as a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. In the update mode, In the update mode, the memory device (either the RCD or the DRAM) can perform configuration of any number of configuration registers with in-band register writes. The in-band register writes can be used to configure decision feedback equalization (DFE) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Abstract: An apparatus is described. The apparatus includes data buffer to memory chip write training circuitry. The data buffer to memory chip write training circuitry to send MDQ/MDQS phase relationship programming information, write commands and read commands to the data buffer chips for multiple write training iterations without a host memory controller having provided the MDQ/MDQS phase relationship programming information, the write commands and the read commands to the data buffer to memory chip write training circuitry.

Abstract: An apparatus is described. The apparatus includes a data buffer chip having write leveling training circuitry. The write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed. Another apparatus is described. The other apparatus includes a registering clock driver (RCD) chip having write leveling training circuitry to determine when to send a write command to a memory chip and a data buffer chip during an external write leveling training process for the memory chip.

Abstract: An integrated circuit includes a buffer circuit, a memory circuit, and a controller circuit that determines if the memory circuit stores information that is valid and determines whether to transmit the information stored in the memory circuit to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit. The controller circuit transmits the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information.

Abstract: Methods and systems are provided for decrypting and/or encryption information received by and/or transmitted from an integrated circuit (IC) device input/output (I/O) interface. A decryption circuit is configurable to apply a first decryption algorithm selected from a plurality of decryption algorithms to received information. An encryption circuit is configurable to apply a first encryption algorithm selected from a plurality of encryption algorithms to transmitted information. A key wrapping circuit is configurable to wrap decryption and/or encryption keys associated with the first decryption and/or encryption algorithm. A firewall circuit is configurable to prevent unauthorized access to the wrapped decryption and/or encryption keys. The decryption and/or encryption circuits are reconfigurable to apply a second decryption algorithm and/or a second encryption algorithm to the received information and/or the transmitted information.

Abstract: A memory module management device and associated apparatus and methods. The device integrates multiple blocks and components on a substrate, including a host input/output (I/O) interface coupled to a host-side port, a power management component, and a device-side I/O interface and router coupled to a plurality of device-side I/O ports. The device is configured to be mounted on a memory module having a plurality of Dynamic Random Access Memory (DRAM) devices that are coupled to the device-side I/O ports and execute firmware instructions on a processing element to facilitate communication between a host in which the memory module is installed and the plurality of DRAM devices using sideband communication. Sideband communication between the host and data buffers and thermal sensors on the memory module are also supported. The device also may be configured to provide scratchpad memory and/or a mailbox. Authentication of the firmware instructions is also supported.

Abstract: According to examples, a memory module with module rows of conductive contacts can enable multiple memory channels to be connected to the same memory module. In one example, a memory module includes a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a connector. The memory module includes a plurality of memory chips on at least one of the first and second faces of the PCB. The memory module includes two or more rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.

Abstract: System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

Abstract: A method, a computer program product, and a system for allocating a variable into storage class memory during compilation of a program. The method includes selecting a variable recorded in a symbol table during compilation and computing a variable size of the variable by analyzing attributes related to the variable. The method further includes computing additional attributes relating to the variable. The method also includes computing a control flow graph and analyzing the control flow graph and the additional attributes to determine an allocation location for the variable. The method further includes allocating the variable into a storage class memory based on the analysis performed.

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.

Abstract: Autonomous QCS and QCA training by the RCD can remove host intervention, freeing the host to handle other tasks while the RCD trains the backside CS and CA buses. In one example, the RCD autonomously trains QCS and/or QCA signal lines by triggering the DRAMs entry into a training mode, driving the signal lines with patterns, and sweeping through delay values for the signal lines. The RCD receives training feedback from the DRAMs over a sideband bus (such as an I3C bus) and programs a delay for the one or more signal lines based on the training feedback. Thus, autonomous QCS and QCA training can reduce training time for every boot by removing host intervention and saving hose cycles.

Abstract: An apparatus is described. The apparatus includes a register clock redriver (RCD) chip comprising a buffer communication (BCOM) interface, a BCOM training control circuit and BCOM training control register space, the BCOM training control circuit is to: transmit a series of symbol transmissions over the BCOM interface to a data buffer with different respective clock phase delays to sweep the symbol transmissions within an eye window; collect resultants of the symbol transmissions from the data buffer; and, perform an analysis on the resultants to determine an appropriate clock phase within the eye window.

Abstract: A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.