Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Abstract: A memory controller circuit includes a first channel circuit having a first programmable switch circuit that is programmable to provide a first request signal indicating a first data access request to a memory circuit. The first programmable switch circuit is programmable to provide a first write data signal indicating first data for storage in the memory circuit. The memory controller circuit includes a second channel circuit having a second programmable switch circuit that is programmable to provide one of the first request signal received from the first programmable switch circuit or a second request signal indicating a second data access request to the memory circuit. The second programmable switch circuit is programmable to provide one of the first write data signal received from the first programmable switch circuit or a second write data signal indicating second data for storage in the memory circuit.

Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Abstract: Method and apparatus for managing memory includes collocating electronic persistent memory along with a primary memory on a memory module. The electronic persistent memory and the primary memory may communicate via a module local bus comprising a plurality of memory channels. A data migration protocol may be used over a memory channel of the plurality of memory channels to copy data from the electronic persistent memory to the primary memory, and the data may be accessed from the primary memory. The combination of electronic persistent memory and primary memory (e.g. DRAM) in a single memory module with module local bus having a device controller running firmware is one implementation of storage class memory (SCM).

Abstract: A method, a computer program product, and a system for allocating a variable into storage class memory during compilation of a program. The method includes selecting a variable recorded in a symbol table during compilation and computing a variable size of the variable by analyzing attributes related to the variable. The method further includes computing additional attributes relating to the variable. The method also includes computing a control flow graph and analyzing the control flow graph and the additional attributes to determine an allocation location for the variable. The method further includes allocating the variable into a storage class memory based on the analysis performed.

Abstract: A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.

Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

Abstract: A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.

Abstract: A method for configuring hardware within a computing system. The method includes one or more computer processors identifying information respectively associated with a plurality of hardware resources within a portion of a computing system. The method further includes determining whether a set of memory modules of differing performance ratings are operatively coupled to a shared bus fabric. The method further includes responding to determining that the set of memory modules of differing performance ratings is operatively coupled to the shared bus fabric by configuring a subsystem to selectively access respective groups of memory modules within the set of memory modules based on a performance rating corresponding to a respective group of memory modules.

Abstract: A computer-implemented method, according to one embodiment, includes: determining a current temperature associated with an intended storage location in memory for data in a write request, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.

Abstract: Method and apparatus for managing memory includes collocating electronic persistent memory along with a primary memory on a memory module. The electronic persistent memory and the primary memory may communicate via a module local bus comprising a plurality of memory channels. A data migration protocol may be used over a memory channel of the plurality of memory channels to copy data from the electronic persistent memory to the primary memory, and the data may be accessed from the primary memory. The combination of electronic persistent memory and primary memory (e.g. DRAM) in a single memory module with module local bus having a device controller running firmware is one implementation of storage class memory (SCM).

Abstract: Predicting physical memory attributes by compiler analysis of code blocks includes receiving source code including at least one code block, and identifying a buffer associated with the at least one code block. Buffer access characteristics associated with the buffer are determined from the at least one code block. The buffer access characteristics are mapped to physical memory attributes associated with one or more physical memories of a computing system. Executable program code including a system call associated with memory allocation is generated based upon the physical memory attribute values.

Abstract: Predicting physical memory attributes by compiler analysis of code blocks includes receiving source code including at least one code block, and identifying a buffer associated with the at least one code block. Buffer access characteristics associated with the buffer are determined from the at least one code block. The buffer access characteristics are mapped to physical memory attributes associated with one or more physical memories of a computing system. Executable program code including a system call associated with memory allocation is generated based upon the physical memory attribute values.

Abstract: A method for configuring hardware within a computing system. The method includes one or more computer processors identifying information respectively associated with a plurality of hardware resources within a portion of a computing system. The method further includes determining whether a set of memory modules of differing performance ratings are operatively coupled to a shared bus fabric. The method further includes responding to determining that the set of memory modules of differing performance ratings is operatively coupled to the shared bus fabric by configuring a subsystem to selectively access respective groups of memory modules within the set of memory modules based on a performance rating corresponding to a respective group of memory modules.

Abstract: Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.

Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: Aspects of the present disclosure relate to a memory module having a volatile memory, a high speed non-volatile memory, and a non-volatile memory. The memory module can allow write mirroring to the volatile memory and high speed non-volatile memory simultaneously. An I/O request is received. A determination is made whether the I/O request is a write or a read. In response to determining that the I/O request is a read, data included in the high speed non-volatile memory is transferred to the non-volatile memory. In response to determining that the I/O request is a write, at least one location to write data of the write is determined based on decoding bits of the write command. The data of the write can then be written to the at least one location.