Patents by Inventor Saravanan Sethuraman

Saravanan Sethuraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10096353
    Abstract: A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, William P. Hovis, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
  • Patent number: 10078587
    Abstract: In one aspect a method includes determining, by a controller of a memory system, that a cache line of one of a plurality of levels of cache in the memory system has been modified. An aspect also includes copying the modified cache line to an auxiliary storage element, and setting a flag in a cache directory for the modified cache line to indicate a cache state of mirrored modified.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: September 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Dell, Shwetha Janardhan, Sairam Kamaraju, Saravanan Sethuraman
  • Patent number: 10075440
    Abstract: In authentication in global attestation, a server receives a request for access to a location based service. The server establishes a connection with a first device and with a second device, wherein the devices are connected by a location bounded network. The server sends a key order information to the first device and a first plurality of keys to the second device. The server receives a second plurality of keys from the first device, wherein the second plurality of keys is an ordered set of keys compiled using the key order information and the first plurality of keys. The server determines that the second plurality of keys received from the first device matches an expected plurality of keys. The server outputs, to the location based service, a notification indicating a result of the determining that the second plurality of keys matches the expected plurality of keys.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Saritha Arunkumar, Diyanesh B. Chinnakkonda Vidyapoornachary, Douglas J. Cowie, Saravanan Sethuraman
  • Patent number: 10067886
    Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Connolly, Joab D. Henderson, Jeffrey A. Sabrowski, Saravanan Sethuraman, Kenneth L. Wright
  • Patent number: 10069829
    Abstract: In authentication in global attestation, a server receives a request for access to a location based service. The server establishes a connection with a first device and with a second device, wherein the devices are connected by a location bounded network. The server sends a key order information to the first device and a first plurality of keys to the second device. The server receives a second plurality of keys from the first device, wherein the second plurality of keys is an ordered set of keys compiled using the key order information and the first plurality of keys. The server determines that the second plurality of keys received from the first device matches an expected plurality of keys. The server outputs, to the location based service, a notification indicating a result of the determining that the second plurality of keys matches the expected plurality of keys.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Saritha Arunkumar, Diyanesh B. Chinnakkonda Vidyapoornachary, Douglas J. Cowie, Saravanan Sethuraman
  • Patent number: 10057276
    Abstract: A method, computer program product, and system for authenticating a computing device by geographic attestation includes a processor utilizing executing an authentication application utilizing location services executing on the computing device to obtain location data from the location services. The processor obtains the location data and creates and encodes a data structure in a secured area of a memory; the data structure is only accessible to the authentication application. The processor transmits to an authentication server, an authentication request that includes the encoded location data, requesting access to secure content. The processor obtains a request to query identifiers proximate to the computing device for additional location information and queries the identifiers and transmits this additional location information to the authentication server.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Saritha Arunkumar, Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman
  • Patent number: 10042726
    Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyu-Hyoun Kim, Warren E. Maule, Kevin M. Mcilvain, Saravanan Sethuraman
  • Patent number: 10025508
    Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Saravanan Sethuraman, Gary A. Tressler
  • Patent number: 9996411
    Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman
  • Publication number: 20180150347
    Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman
  • Publication number: 20180151246
    Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Inventors: Michael B. Healy, Hillery C. Hunter, Janani Mukundan, Karthick Rajamani, Saravanan Sethuraman
  • Publication number: 20180150369
    Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.
    Type: Application
    Filed: December 14, 2017
    Publication date: May 31, 2018
    Inventors: Kyu-Hyoun Kim, Warren E. Maule, Kevin M. Mcilvain, Saravanan Sethuraman
  • Patent number: 9972376
    Abstract: A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, William P. Hovis, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
  • Patent number: 9965017
    Abstract: A computer-implemented method for controlling power consumption in a non-volatile dual inline memory module (NVDIMM-N) may include determining, via a processor, whether the NVDIMM-N is receiving power from a main power source, inactivating, via the processor, a data bus connected to an NVDIMM-N memory group responsive to determining that the NVDIMM-N is not receiving power from the main power source, backing up data stored in the NVDIMM-N memory group, via the processor, to a non-volatile memory module integrated with the NVDIMM-N, where an NVDIMM-N controller can access the NVDIMM-N memory group while backing up, and transmitting, via the processor, a low power command to an NVDIMM-N controller to place the NVDIMM-N memory group in a low power mode.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: May 8, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Saravanan Sethuraman, Gary A. Tressler
  • Publication number: 20180103021
    Abstract: Embodiments disclose systems, methods, and computer program products to perform an operation for adapting a set of devices used to authenticate a client device. The operation generally includes determining a plurality of broker devices available for attesting a location of a client device, and determining, from the available broker devices, a first and second subset of broker devices based on a credibility score determined for each of the available broker devices. The operation also includes attesting the location of the client device based on information received from the first subset of broker devices regarding devices in proximity to each of the broker devices in the first subset. The operation further includes upon determining that a number of responses with the information from at least one of the broker devices in the first subset has reached a threshold, reassigning broker devices in the first and second subsets.
    Type: Application
    Filed: October 7, 2016
    Publication date: April 12, 2018
    Inventors: Saritha ARUNKUMAR, Diyanesh B. Chinnakkonda Vidyapoornachary, Douglas J. COWIE, Farheen MUNSHI, Saravanan SETHURAMAN
  • Publication number: 20180102176
    Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 12, 2018
    Inventors: Saravanan SETHURAMAN, Gary A. TRESSLER, Harish VENKATARAMAN
  • Publication number: 20180083981
    Abstract: A method, computer program product, and system for authenticating a computing device by geographic attestation includes a processor utilizing executing an authentication application utilizing location services executing on the computing device to obtain location data from the location services. The processor obtains the location data and creates and encodes a data structure in a secured area of a memory; the data structure is only accessible to the authentication application. The processor transmits to an authentication server, an authentication request that includes the encoded location data, requesting access to secure content. The processor obtains a request to query identifiers proximate to the computing device for additional location information and queries the identifiers and transmits this additional location information to the authentication server.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Saritha Arunkumar, Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman
  • Patent number: 9921623
    Abstract: A method, system and computer program product for implementing thermal air flow control management of a computer system. A temperature profile of the server system is identified. One or more dual in-line memory-modules (DIMMs) are used to pivot on an axis to direct air flow to cool identified hot spots based upon the temperature profile of the server system.
    Type: Grant
    Filed: April 25, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Saravanan Sethuraman
  • Patent number: 9915987
    Abstract: A method, system and computer program product for implementing thermal air flow control management of a computer system. A temperature profile of the server system is identified. One or more dual in-line memory-modules (DIMMs) are used to pivot on an axis to direct air flow to cool identified hot spots based upon the temperature profile of the server system.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Saravanan Sethuraman
  • Publication number: 20180067874
    Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.
    Type: Application
    Filed: November 8, 2017
    Publication date: March 8, 2018
    Inventors: Brian J. Connolly, Joab D. Henderson, Jeffrey A. Sabrowski, Saravanan Sethuraman, Kenneth L. Wright