Patents by Inventor Sarma Sundareswara Gunturi

Sarma Sundareswara Gunturi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10505582
    Abstract: Signal compression for serialized data bandwidth reduction based on decomposition of a data signal into separate signal components with different SQNR or dynamic range requirements, and quantizing the signal components with different bit precisions. Compression logic decomposes the input data signal into the first/second signal components, quantizes the first component with a pre-defined first bit precision to provide a first quantized data signal, quantizes the second component with a pre-defined second bit precision to provide a second quantized data signal, the second bit precision less than the first bit precision, the first and second quantized data signals bit packed into a compressed digital data signal.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sarma Sundareswara Gunturi, Jaiganesh Balakrishnan
  • Patent number: 10484224
    Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Sarma Sundareswara Gunturi, Pankaj Gupta, Indu Prathapan
  • Publication number: 20190273601
    Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Jaiganesh BALAKRISHNAN, Shagun DUSAD, Visvesvaraya PENTAKOTA, Srinivas Kumar Reddy NARU, Sarma Sundareswara GUNTURI, Nagalinga Swamy Basayya AREMALLAPUR
  • Publication number: 20190207612
    Abstract: A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.
    Type: Application
    Filed: April 10, 2018
    Publication date: July 4, 2019
    Inventors: Sarma Sundareswara GUNTURI, Sundarrajan RANGACHARI, Aswath VS, Raunak DHANIWALA
  • Patent number: 10341082
    Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Shagun Dusad, Visvesvaraya Pentakota, Srinivas Kumar Reddy Naru, Sarma Sundareswara Gunturi, Nagalinga Swamy Basayya Aremallapur
  • Patent number: 10341953
    Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Sarma Sundareswara Gunturi
  • Publication number: 20190175037
    Abstract: An apparatus to detect a heart rate of a user includes a motion detection circuit configured to generate a motion status signal indicative of a motion status of the user. The apparatus also comprises a filter circuit coupled to the motion detection circuit that is configured to generate a filter circuit output signal based on dynamically variable. The coefficients are dependent on the motion status signal and a first signal received by the filter circuit. The apparatus also comprises a combination circuit coupled to the filter circuit and configured to receive a second signal indicative of the ambient light, the motion of the user, and non-ambient light reflected from the user. The combination circuit is configured to determine a difference between the second signal and the filter circuit output signal to generate a combination circuit output signal.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 13, 2019
    Inventors: Sarma Sundareswara GUNTURI, Jaiganesh BALAKRISHNAN
  • Publication number: 20190068238
    Abstract: Signal compression for serialized data bandwidth reduction based on decomposition of a data signal into separate signal components with different SQNR or dynamic range requirements, and quantizing the signal components with different bit precisions. Compression logic decomposes the input data signal into the first/second signal components, quantizes the first component with a pre-defined first bit precision to provide a first quantized data signal, quantizes the second component with a pre-defined second bit precision to provide a second quantized data signal, the second bit precision less than the first bit precision, the first and second quantized data signals bit packed into a compressed digital data signal.
    Type: Application
    Filed: March 23, 2018
    Publication date: February 28, 2019
    Inventors: Sarma Sundareswara Gunturi, Jaiganesh Balakrishnan
  • Publication number: 20190053763
    Abstract: The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Sarma Sundareswara Gunturi, Sunil Chomal
  • Patent number: 10123746
    Abstract: The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: November 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sarma Sundareswara Gunturi, Sunil Chomal
  • Publication number: 20180227157
    Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Jaiganesh Balakrishnan, Sarma Sundareswara Gunturi, Pankaj Gupta, Indu Prathapan
  • Patent number: 9967123
    Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: May 8, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Sarma Sundareswara Gunturi, Pankaj Gupta, Indu Prathapan
  • Publication number: 20180035375
    Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 1, 2018
    Inventors: Jaiganesh Balakrishnan, Sarma Sundareswara Gunturi
  • Patent number: 9820230
    Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: November 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Sarma Sundareswara Gunturi
  • Publication number: 20170078970
    Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.
    Type: Application
    Filed: September 11, 2015
    Publication date: March 16, 2017
    Inventors: Jaiganesh BALAKRISHNAN, Sarma Sundareswara GUNTURI
  • Publication number: 20160324477
    Abstract: The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 10, 2016
    Inventors: Sarma Sundareswara GUNTURI, Sunil CHOMAL
  • Patent number: 9491012
    Abstract: Example embodiments of systems and methods of direct oversampled low PAR pulse shaping encapsulating DSSS spreading are disclosed herein. Pulse-shaping of a DSSS spread data symbol stream results in a small number of waveform patterns to choose from for any data-symbol window. Low complexity programmable look-up table (LUT) based direct pulse shaping may be implemented, while only needing to compute a negation function. The chosen pulse shape may generate a low PAR for the baseband signal, allowing for a reduction in the saturation power of the power amplifier, thereby reducing the overall transmitter power consumption.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 8, 2016
    Assignee: Texas Instruments Incorporated
    Inventors: Jaiganesh Balakrishnan, Sriram Murali, Sundarrajan Rangachari, Sarma Sundareswara Gunturi
  • Patent number: 9484979
    Abstract: A wireless transceiver decodes a receive signal to extract data contained in the receive signal. A processing block contained in the wireless transceiver then initiates a power-ON of the transmit radio portions of the transceiver prior to initiating a power-OFF of the receive radio portions. The technique enables the transceiver to meet timing requirements when operating in environments that require an acknowledgement to be sent in response to receipt of data.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: November 1, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saurabh Khanna, Sarma Sundareswara Gunturi, Vijaya Sarathy Bergai ParthaSarathy