Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

Abstract: A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.

Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.

Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

Abstract: An apparatus to detect a heart rate of a user includes a motion detection circuit configured to generate a motion status signal indicative of a motion status of the user. The apparatus also comprises a filter circuit coupled to the motion detection circuit that is configured to generate a filter circuit output signal based on dynamically variable. The coefficients are dependent on the motion status signal and a first signal received by the filter circuit. The apparatus also comprises a combination circuit coupled to the filter circuit and configured to receive a second signal indicative of the ambient light, the motion of the user, and non-ambient light reflected from the user. The combination circuit is configured to determine a difference between the second signal and the filter circuit output signal to generate a combination circuit output signal.

Abstract: Signal compression for serialized data bandwidth reduction based on decomposition of a data signal into separate signal components with different SQNR or dynamic range requirements, and quantizing the signal components with different bit precisions. Compression logic decomposes the input data signal into the first/second signal components, quantizes the first component with a pre-defined first bit precision to provide a first quantized data signal, quantizes the second component with a pre-defined second bit precision to provide a second quantized data signal, the second bit precision less than the first bit precision, the first and second quantized data signals bit packed into a compressed digital data signal.

Abstract: The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.

Abstract: The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.

Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.

Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.

Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.

Abstract: The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.

Abstract: Example embodiments of systems and methods of direct oversampled low PAR pulse shaping encapsulating DSSS spreading are disclosed herein. Pulse-shaping of a DSSS spread data symbol stream results in a small number of waveform patterns to choose from for any data-symbol window. Low complexity programmable look-up table (LUT) based direct pulse shaping may be implemented, while only needing to compute a negation function. The chosen pulse shape may generate a low PAR for the baseband signal, allowing for a reduction in the saturation power of the power amplifier, thereby reducing the overall transmitter power consumption.

Abstract: A wireless transceiver decodes a receive signal to extract data contained in the receive signal. A processing block contained in the wireless transceiver then initiates a power-ON of the transmit radio portions of the transceiver prior to initiating a power-OFF of the receive radio portions. The technique enables the transceiver to meet timing requirements when operating in environments that require an acknowledgement to be sent in response to receipt of data.