Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

Abstract: An apparatus to detect a heart rate of a user includes a motion detection circuit configured to generate a motion status signal indicative of a motion status of the user. The apparatus also comprises a filter circuit coupled to the motion detection circuit that is configured to generate a filter circuit output signal based on dynamically variable. The coefficients are dependent on the motion status signal and a first signal received by the filter circuit. The apparatus also comprises a combination circuit coupled to the filter circuit and configured to receive a second signal indicative of the ambient light, the motion of the user, and non-ambient light reflected from the user. The combination circuit is configured to determine a difference between the second signal and the filter circuit output signal to generate a combination circuit output signal.

Abstract: One example includes a receiver system. The receiver system includes an analog-to-digital converter (ADC) configured to convert an analog input signal into a digital output signal at a sampling frequency. The receiver system also includes a spur correction system configured to receive the digital output signal and to estimate spurs associated with the digital output signal and to selectively correct a subset of the spurs associated with a set of frequencies that are based on the sampling frequency.

Abstract: An IQ mismatch estimation circuit includes a raw channel estimation circuit, a reference channel estimation circuit, a digital predistortion (DPD) bin identification circuit, a channel estimate pruning circuit, and an IQ correction coefficient generation circuit. The raw channel estimation circuit generates raw channel estimates for a plurality of frequency bins of a baseband signal. The reference channel estimation circuit identifies a reference channel estimate based on the raw channel estimates. The DPD bin identification circuit identifies, based on the reference channel estimate, the frequency bins for which the raw channel estimates are based on a DPD expansion signal. The channel estimate pruning circuit generates pruned raw channel estimates by discarding the raw channel estimates of the frequency bins identified by the DPD bin identification circuit. The IQ correction coefficient generation circuit generates IQ mismatch correction coefficients based on the pruned raw channel estimates.

Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.

Abstract: An apparatus to detect a heart rate of a user includes a motion detection circuit configured to generate a motion status signal indicative of a motion status of the user. The apparatus also comprises a filter circuit coupled to the motion detection circuit that is configured to generate a filter circuit output signal based on dynamically variable. The coefficients are dependent on the motion status signal and a first signal received by the filter circuit. The apparatus also comprises a combination circuit coupled to the filter circuit and configured to receive a second signal indicative of the ambient light, the motion of the user, and non-ambient light reflected from the user. The combination circuit is configured to determine a difference between the second signal and the filter circuit output signal to generate a combination circuit output signal.

Abstract: The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.

Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.

Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.

Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.

Abstract: The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.

Abstract: An electrical system includes a transceiver with an IQ estimator and an IQ mismatch corrector. The electrical system also includes an antenna coupled to the transceiver. The IQ estimator is configured to perform frequency-domain IQ mismatch analysis to determine an IQ mismatch estimate at available frequency bins of a baseband data signal. The IQ mismatch corrector is configured to correct the baseband data signal based on the IQ mismatch estimate.

Abstract: A phase spectrum based delay estimating method of tracking channel responses, extracting phase responses from the tracked channel responses, and generating a delay estimate, wherein the delay estimate is based on a slope and intercept estimates of the extracted phase responses with high quality metric to improve delay estimation, and a system thereof.

Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.

Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.

Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.

Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.

Abstract: A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.

Abstract: Signal compression for serialized data bandwidth reduction based on decomposition of a data signal into separate signal components with different SQNR or dynamic range requirements, and quantizing the signal components with different bit precisions. Compression logic decomposes the input data signal into the first/second signal components, quantizes the first component with a pre-defined first bit precision to provide a first quantized data signal, quantizes the second component with a pre-defined second bit precision to provide a second quantized data signal, the second bit precision less than the first bit precision, the first and second quantized data signals bit packed into a compressed digital data signal.