Patents by Inventor Sasan Cyrusian

Sasan Cyrusian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9985804
    Abstract: A receiver includes a first sampler configured to sample, according to a first clock signal, a received signal including first data and second data and output first samples corresponding to the first data of the received signal. A first data comparator is configured to receive, from the first sampler, the first samples corresponding to the first data of the received signal and generate, based on the first clock signal, a first digital data output corresponding to the first data of the received signal. A first error comparator is configured to receive, from the first sampler, the first samples corresponding to the first data of the received signal and generate, based on the first clock signal, a first digital error output corresponding to the first data of the received signal and a first error associated with the first data of the received signal.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 29, 2018
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 9941872
    Abstract: An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 10, 2018
    Assignee: Marvell International Ltd.
    Inventor: Sasan Cyrusian
  • Publication number: 20170077917
    Abstract: An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.
    Type: Application
    Filed: November 22, 2016
    Publication date: March 16, 2017
    Inventor: Sasan CYRUSIAN
  • Patent number: 9501133
    Abstract: A method including: accounting for a transition time for a device to transition between two of first, second, and powered off states; generating a control signal based on the transition time; receiving, at the device and from a processor, an output signal and the control signal; and consuming power, via the device, while operating in the first state and the second state. The method further includes: in response to the control signal, transitioning the device to the second state based on a frequency of the output signal or the control signal; subsequent to transitioning to the second state, performing a function based on the first output signal; and subsequent to performing the function, generating an output via the device; generating a feedback signal based on the output; and based on the feedback signal, transitioning the device to either the first state or the powered off state.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 22, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 9503069
    Abstract: An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: November 22, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventor: Sasan Cyrusian
  • Publication number: 20160285655
    Abstract: A receiver includes a first sampler configured to sample, according to a first clock signal, a received signal including first data and second data and output first samples corresponding to the first data of the received signal. A first data comparator is configured to receive, from the first sampler, the first samples corresponding to the first data of the received signal and generate, based on the first clock signal, a first digital data output corresponding to the first data of the received signal. A first error comparator is configured to receive, from the first sampler, the first samples corresponding to the first data of the received signal and generate, based on the first clock signal, a first digital error output corresponding to the first data of the received signal and a first error associated with the first data of the received signal.
    Type: Application
    Filed: June 8, 2016
    Publication date: September 29, 2016
    Inventor: Sasan Cyrusian
  • Patent number: 9367385
    Abstract: A receiver path including first, second, third, and fourth comparator modules. The first comparator module is configured to generate, based on a signal received via the receiver path, a first digital output signal indicative of a sum of first data in the received signal and a first error. The second comparator module is configured to generate, based on the signal received via the receiver path, a second digital output signal indicative of a sum of second data in the received signal and a second error. The third comparator module is configured to generate, based on the signal received via the receiver path, a third digital output signal indicative of the first data in the received signal. The fourth comparator module is configured to generate, based on the signal received via the receiver path, a fourth digital output signal indicative of the second data in the received signal.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: June 14, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 9350331
    Abstract: A latch includes a current source, an input amplifier, and a latch output circuit. The current source is configured to output a current based on a voltage source. The input amplifier is configured to receive a differential analog input signal including a first differential input and a second differential input and selectively provide the current based on the first differential input and the second differential input. A latch output circuit is configured to selectively output a differential digital output signal including a first differential output and a second differential output. The latch output circuit includes an over voltage protection circuit configured to receive the current output from the input amplifier, receive the voltage source limit, and output a modified differential digital output signal based on a comparison between a voltage corresponding to each of the first differential output and the second differential output and the voltage source limit.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 24, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 9130582
    Abstract: A system including a converter, a buffer, and an offset adjust circuit. The converter is configured to provide, based on a digital input signal, a first output current. The buffer is configured to provide, based on the first output current, a second output current to an output pin. The offset adjust circuit is in communication with the first output current and is configured to, based on the second current at the output pin, adjust the first output current to compensate for a current offset at the output pin.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: September 8, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Sasan Cyrusian
  • Patent number: 9088273
    Abstract: Systems, methods, and other embodiments associated with estimating a natural sampling point from uniform sample points when generating a PWM signal are described. According to one embodiment, an apparatus includes a cross point logic configured to determine which of the samples along the analog signal are adjacent to a crossing point of a reference signal and the analog signal by identifying samples between which the crossing point occurs. The apparatus includes an interpolation logic configured to adaptively interpolate points along the analog signal that approach the crossing point by using the samples. The interpolation logic is configured to adaptively interpolate the points to refine a region between the points within which the crossing point occurs. The apparatus includes a search logic configured to search within the region to produce an estimated location of the crossing point by using the interpolated points.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: July 21, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Sasan Cyrusian, Zining Wu, Kapil Jain
  • Patent number: 9059874
    Abstract: An apparatus includes an input, an output, an equalizer configured to receive an input signal at the input and to output an output signal for the output, and a reset block coupled to the equalizer and the output. The reset block is configured to pull the output signal at the output toward a bias voltage level based on a reset signal.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: June 16, 2015
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 9049068
    Abstract: An equalizer includes a first module and a second module. The first module is configured to receive a differential input signal, perform low pass filtering on the differential input signal to generate a low pass differential input signal, and perform high pass filtering on the differential input signal to generate a high pass differential input signal. The second module is configured to receive the low pass differential input signal and the high pass differential input signal and generate a differential output signal based on a combination of the low pass differential input signal and the high pass differential input signal.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: June 2, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventor: Sasan Cyrusian
  • Patent number: 8937508
    Abstract: Aspects of the disclosure provide a differential amplifier. The differential amplifier includes a first pair of complementary transistors, a second pair of complementary transistors, and a current source. First control terminals of the first pair of complementary transistors are coupled to a first input node of the differential amplifier and first driving terminals of the first pair of complementary transistors are coupled to a first output node of the differential amplifier for driving a load. Second control terminals of the second pair of complementary transistors are coupled to a second input node of the differential amplifier and second driving terminals of the second pair of complementary transistors coupled to a second output node of the differential amplifier for driving the load. The current source is configured to maintain a substantially constant total current flow through the first pair of complementary transistors and the second pair of complementary transistors.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: January 20, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sasan Cyrusian, Gregory T. Uehara
  • Publication number: 20150012770
    Abstract: A method including: accounting for a transition time for a device to transition between two of first, second, and powered off states; generating a control signal based on the transition time; receiving, at the device and from a processor, an output signal and the control signal; and consuming power, via the device, while operating in the first state and the second state. The method further includes: in response to the control signal, transitioning the device to the second state based on a frequency of the output signal or the control signal; subsequent to transitioning to the second state, performing a function based on the first output signal; and subsequent to performing the function, generating an output via the device; generating a feedback signal based on the output; and based on the feedback signal, transitioning the device to either the first state or the powered off state.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventor: Sasan Cyrusian
  • Patent number: 8841961
    Abstract: An apparatus includes a processor and a device. The processor generates an output signal and a control signal. The device consumes power while operating in first and second states. The device consumes less power while in the first state than while in the second state. The processor: accounts for a transition time for the device to transition among a powered off state, the first state, and the second state; and generates the control signal based on the transition time. The device: in response to the control signal, transitions to the second state at a speed of periodicity of a periodic signal of the processor; subsequent to the transitioning to the second state, performs a function based on the output signal; and subsequent to performing the function, transitions from the second state to either the first state or the powered off state.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 23, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Publication number: 20140281845
    Abstract: A receiver path including first, second, third, and fourth comparator modules. The first comparator module is configured to generate, based on a signal received via the receiver path, a first digital output signal indicative of a sum of first data in the received signal and a first error. The second comparator module is configured to generate, based on the signal received via the receiver path, a second digital output signal indicative of a sum of second data in the received signal and a second error. The third comparator module is configured to generate, based on the signal received via the receiver path, a third digital output signal indicative of the first data in the received signal. The fourth comparator module is configured to generate, based on the signal received via the receiver path, a fourth digital output signal indicative of the second data in the received signal.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 18, 2014
    Applicant: Marvell World Trade Ltd.
    Inventor: Sasan CYRUSIAN
  • Publication number: 20140268450
    Abstract: A latch includes a current source, an input amplifier, and a latch output circuit. The current source is configured to output a current based on a voltage source. The input amplifier is configured to receive a differential analog input signal including a first differential input and a second differential input and selectively provide the current based on the first differential input and the second differential input. A latch output circuit is configured to selectively output a differential digital output signal including a first differential output and a second differential output. The latch output circuit includes an over voltage protection circuit configured to receive the current output from the input amplifier, receive the voltage source limit, and output a modified differential digital output signal based on a comparison between a voltage corresponding to each of the first differential output and the second differential output and the voltage source limit.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Marvell World Trade LTD.
    Inventor: Sasan Cyrusian
  • Patent number: 8816763
    Abstract: A circuit includes a first amplifier and a second amplifier, wherein first amplifier is configured to receive an input current at a first input of the first amplifier, and an output of the first op-mp is configured to drive a first input of the second amplifier. The circuit further includes a pull-up current source selectively coupled to the first input of the second amplifier, and a pull-down current source selectively coupled to the first input of the second amplifier. If the absolute value of the input current is larger than a predefined threshold current: i) the pull-up current source is configured to drive current into the first input of the second amplifier for a first polarity of the input current, and ii) the pull-down current source is configured to sink current from the first input of the second amplifier for a second polarity of the input current.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 26, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Publication number: 20140059364
    Abstract: An apparatus includes a processor and a device. The processor generates an output signal and a control signal. The device consumes power while operating in first and second states. The device consumes less power while in the first state than while in the second state. The processor: accounts for a transition time for the device to transition among a powered off state, the first state, and the second state; and generates the control signal based on the transition time. The device: in response to the control signal, transitions to the second state at a speed of periodicity of a periodic signal of the processor; subsequent to the transitioning to the second state, performs a function based on the output signal; and subsequent to performing the function, transitions from the second state to either the first state or the powered off state.
    Type: Application
    Filed: November 4, 2013
    Publication date: February 27, 2014
    Applicant: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Publication number: 20140050260
    Abstract: An apparatus includes an input, an output, an equalizer configured to receive an input signal at the input and to output an output signal for the output, and a reset block coupled to the equalizer and the output. The reset block is configured to pull the output signal at the output toward a bias voltage level based on a reset signal.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 20, 2014
    Applicant: Marvell World Trade Ltd.
    Inventor: Sasan CYRUSIAN