Abstract: An apparatus includes an input, an output, an equalizer configured to receive an input signal at the input and to output an output signal for the output, and a reset block coupled to the equalizer and the output. The reset block is configured to pull the output signal at the output toward a bias voltage level based on a reset signal.

Abstract: A circuit includes a first amplifier and a second amplifier, wherein first amplifier is configured to receive an input current at a first input of the first amplifier, and an output of the first op-mp is configured to drive a first input of the second amplifier. The circuit further includes a pull-up current source selectively coupled to the first input of the second amplifier, and a pull-down current source selectively coupled to the first input of the second amplifier. If the absolute value of the input current is larger than a predefined threshold current: i) the pull-up current source is configured to drive current into the first input of the second amplifier for a first polarity of the input current, and ii) the pull-down current source is configured to sink current from the first input of the second amplifier for a second polarity of the input current.

Abstract: A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differential stage to a low-power state. The periodically increasing of the tail current and the periodically decreasing of the tail current are asynchronous operations for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state. Periodically increasing the tail current and the periodically decreasing the tail current asynchronously for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state provide for low noise and high speed during signal comparison.

Abstract: The present disclosure provides for improved DAC circuits and methods. In one embodiment, a digital-to-analog converter receives a digital signal and outputs a first analog output signal corresponding to the digital signal. A current buffer receives the first analog output signal and generates an analog output current. The current output digital-to-analog converter and the current buffer are constructed on an integrated circuit, and the analog output current is coupled to a pin of the integrated circuit. The pin of the integrated circuit receives the analog output current and provides the analog output current to additional circuitry external to the integrated circuit.

Abstract: A circuit includes a first amplifier and a second amplifier, wherein first amplifier is configured to receive an input current at a first input of the first amplifier, and an output of the first op-mp is configured to drive a first input of the second amplifier. The circuit further includes a pull-up current source selectively coupled to the first input of the second amplifier, and a pull-down current source selectively coupled to the first input of the second amplifier. If the absolute value of the input current is larger than a predefined threshold current: i) the pull-up current source is configured to drive current into the first input of the second amplifier for a first polarity of the input current, and ii) the pull-down current source is configured to sink current from the first input of the second amplifier for a second polarity of the input current.

Abstract: Systems, methods, and other embodiments associated with estimating a natural sampling point from uniform sample points when generating a PWM signal are described. According to one embodiment, an apparatus includes a cross point logic configured to determine which of the samples along the analog signal are adjacent to a crossing point of a reference signal and the analog signal by identifying samples between which the crossing point occurs. The apparatus includes an interpolation logic configured to adaptively interpolate points along the analog signal that approach the crossing point by using the samples. The interpolation logic is configured to adaptively interpolate the points to refine a region between the points within which the crossing point occurs. The apparatus includes a search logic configured to search within the region to produce an estimated location of the crossing point by using the interpolated points.

Abstract: A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differential stage to a low-power state. The periodically increasing of the tail current and the periodically decreasing of the tail current are asynchronous operations for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state. Periodically increasing the tail current and the periodically decreasing the tail current asynchronously for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state provide for low noise and high speed during signal comparison.

Abstract: A circuit includes a first amplifier and a second amplifier, wherein first amplifier is configured to receive an input current at a first input of the first amplifier, and an output of the first op-mp is configured to drive a first input of the second amplifier. The circuit further includes a pull-up current source selectively coupled to the first input of the second amplifier, and a pull-down current source selectively coupled to the first input of the second amplifier. If the absolute value of the input current is larger than a predefined threshold current: i) the pull-up current source is configured to drive current into the first input of the second amplifier for a first polarity of the input current, and ii) the pull-down current source is configured to sink current from the first input of the second amplifier for a second polarity of the input current.

Abstract: The present disclosure provides for improved DAC circuits and methods. In one embodiment, a digital-to-analog converter receives a digital signal and outputs a first analog output signal corresponding to the digital signal. A current buffer receives the first analog output signal and generates an analog output current. The current output digital-to-analog converter and the current buffer are constructed on an integrated circuit, and the analog output current is coupled to a pin of the integrated circuit. The pin of the integrated circuit receives the analog output current and provides the analog output current to additional circuitry external to the integrated circuit.

Abstract: In one embodiment the present invention includes circuits and methods for calibrating switching current sources. A difference between a source current and a sink current is detected during a calibration phase. The difference is used to generate a digital signal to adjust a programmable current source to reduce the difference between currents. In one embodiment, a binary search is used to generate the digital signal during an initial calibration phase, and a linear approximation is used to generate the digital signal during an operational calibration phase.

Abstract: A noise shaper truncates the widths of pulses it supplies to a pulse-width modulator whose pulse-width modulated signals control a tri-level amplifier. The amplifier is filterless and DC free. Pulses that are narrower than a predefined minimum width are eliminated by the noise shaper. Other pulses are subjected to an algorithm that includes a multitude of ranges, each range defined by a minimum pulse width characterizing a lower bound of that range and a maximum pulse width characterizing an upper bound of that range. Associated with each range is a number of clock cycles defining the modified width of a pulses whose detected width falls within that range. To ensure that delays associated with a feedback loop disposed in the amplifier are accounted for, the reference voltage of a comparator tracks an output voltage of an integrator. Both the comparator and integrator are disposed in the loop.

Abstract: An amplifier generates a tri-level output signal in response to an input signal that is pulse-width modulated. The amplifier is filterless and DC free. A control block supplies a multitude of pulse-width modulated (PWM) signals in response to the received digital input signal. A pair of the PWM signals are applied to the signal generator which in response supplies a third signal to the integrator. The integrator integrates the third signal in accordance with a feedback signal.

Abstract: An amplifier generates a tri-level output signal in response to an input signal that is pulse-width modulated. The amplifier is filterless and DC free. A control block supplies a multitude of pulse-width modulated (PWM) signals in response to the received digital input signal. A pair of the PWM signals are applied to the signal generator which in response supplies a third signal to the integrator. The integrator integrates the third signal in accordance with a feedback signal.

Abstract: A noise shaper truncates the widths of pulses it supplies to a pulse-width modulator whose pulse-width modulated signals control a tri-level amplifier. The amplifier is filterless and DC free. Pulses that are narrower than a predefined minimum width are eliminated by the noise shaper. Other pulses are subjected to an algorithm that includes a multitude of ranges, each range defined by a minimum pulse width characterizing a lower bound of that range and a maximum pulse width characterizing an upper bound of that range. Associated with each range is a number of clock cycles defining the modified width of a pulses whose detected width falls within that range. To ensure that delays associated with a feedback loop disposed in the amplifier are accounted for, the reference voltage of a comparator tracks an output voltage of an integrator. Both the comparator and integrator are disposed in the loop.

Abstract: A current steering circuit includes a multitude of current stages each including an associated current source transistor, and first and second cascode transistors coupled in series with the associated current source transistor. The first and second cascode transistors respectively receive first and second reference voltages and are biased such that a voltage appearing across any terminal pairs of the transistors is less than a predefined value. Each current stage includes a first switch supplying the current flowing through the transistors to a first resistive load in response to a control signal, and a second switch supplying the current to a second resistive load in response to a complement of the control signal. An amplifier responsive to an analog multiplexer's output provides a biasing voltage to each of the current stages. The analog multiplexer supplies a different output voltage in response to different counts of a counter.

Abstract: A digital-to-analog converter is described. The digital-to-analog converter converts an m-bit digital signal into an analog signal using m weighted currents, such as m binary-weighted currents. A first weighted current may be calibrated using a reference current. The first weighted current may be compared to the reference current, and a control signal, controlling the first weighted current, may be generated to adjust the first weighted current to be substantially equal to the reference current. The first weighted current may then be compared with another of the m weighted currents (such as a second weighted current). The comparison may be used to further calibrate the first weighted current or to calibrate the second weighted current.

Abstract: Apparatus having corresponding methods comprise: a first fixed current source to produce a first fixed current; a second fixed current source to produce a second fixed current; a first adjustable current source to produce a first adjustable current; a first switch to deliver the first fixed current and the first adjustable current to a first output node when the first switch is closed; a second switch to deliver the second fixed current to the first output node when the second switch is closed; and an adjustment circuit to adjust the first adjustable current according to the first fixed current, the second fixed current, and the adjustable current.

Abstract: An amplifier generates a tri-level output signal in response to an input signal that is pulse-width modulated. The amplifier is filterless and DC free. The amplifier includes an integrator, a signal generator, comparator, a switch pulse logic block, a driver, and a control block. The control block supplies a multitude of pulse-width modulated (PWM) signals in response to the received digital input signal. A pair of the PWM signals are applied to the signal generator which in response supplies a signal to the integrator. The integrator's output signal is compared to a reference signal by the comparator. The switch pulse logic block receives the output of the comparator and a pair of delayed PWM signals and in response generates a multitude of driver signals applied to the driver. The driver supplies an output signal that is adapted to vary between first, second and third voltages.

Abstract: A current steering circuit includes a multitude of current stages each including an associated current source transistor, and first and second cascode transistors coupled in series with the associated current source transistor. The first and second cascode transistors respectively receive first and second reference voltages and are biased such that a voltage appearing across any terminal pairs of the transistors is less than a predefined value. Each current stage includes a first switch supplying the current flowing through the transistors to a first resistive load in response to a control signal, and a second switch supplying the current to a second resistive load in response to a complement of the control signal. An amplifier responsive to an analog multiplexer's output provides a biasing voltage to each of the current stages. The analog multiplexer supplies a different output voltage in response to different counts of a counter.

Abstract: A method and apparatus for calibrating a Gm cell using a Gm replica cell. A digital to analog converter receives a Gm setting code and generates a reference current. The Gm replica cell adjusts the tuning voltage until the difference between a pair of drain currents is substantially equal to the reference current. Where this condition is satisfied, the proper tuning voltage has been acquired. This results in proper calibration for the tuning voltage, which then may be utilized by a Gm cell connected with the Gm replica cell.